I wonder if this is where the system is looking for the hardware AFG...(From @s2084's modified HW8)
(Attachment Link)
Does anyone have the console log output from a real 924S?
Reason I ask:
(Attachment Link) HW12 (Attachment Link) HW8 -Mod
i managed to get an "older" version of IDA and disassemble afg_gpio.ko... looks like another can of worm of 5 bits config resistor? but am struggling to learn ARM ASM code here... not sure whats those "0x7A" to "0x7E" representing... i need to sleep now, hopefully will continue this afternoon ...
The following is the logical pseudocode for a few key functions:
int gpio_afg_init(){
set GPIO_122 Label is afg__in1
set GPIO_122 Output Low
set GPIO_123 Label is afg__in2
set GPIO_123 Output Low
set GPIO_124 Label is afg__in3
set GPIO_124 Output Low
set GPIO_125 Label is afg__in4
set GPIO_125 Output Low
set GPIO_126 Label is afg__in5
set GPIO_126 Output Low
}
ssize_t gpio_afg_drv_write(file *file, const int8 *buf, size_t len, loff_t *f_pos){
1.copy user data to core.
_arch_copy_from_user(*DB,*buf ,len);
2.write GPIO value.
write GPIO_122(afg__in1) is DB[0] bit value.
write GPIO_123(afg__in2) is DB[1] bit value.
write GPIO_124(afg__in3) is DB[2] bit value.
write GPIO_125(afg__in4) is DB[3] bit value.
write GPIO_126(afg__in5) is DB[4] bit value.
}
ssize_t gpio_afg_drv_read(file *file, int8 *buf, size_t len, loff_t *f_pos){
1.read DB from GPIO value.
read DB[0] from GPIO_122(afg__in1) bit value.
read DB[1] from GPIO_123(afg__in2) bit value.
read DB[2] from GPIO_124(afg__in3) bit value.
read DB[3] from GPIO_125(afg__in4) bit value.
read DB[4] from GPIO_126(afg__in5) bit value.
2. copy core DB to user.
_arch_copy_to_user(buf, DB,len);
}
The following is the logical pseudocode for a few key functions.
It is still unclear how the RK3399 GPIO_122~GPIO_126 corresponds to the pins of the AD9744 DAC, and you need to explore. Good luck!