Three photos of underside of CPU in original & unmodified DHO924S. If somebody wants more photos of something particular - better tell me now.
Could you take a photo of the side of the input tract?(Its analog part)
Input stages? I already did. First things first. Now Im removing LC filter from channel 4 and adding missing capacitors around dc-dc converters - some of them wasnt populated (one instead of two parallel).
Ścieżka wejścia analogowego
More like: stopień wejścia analogowego. Word ścieżka means path.
BW 400-500MHz maybe sensible, but 800MHz BW maybe not because nyquist is 1.6-2GSps, way more even using single CH, unless if you can hack/boost the sample rate.
my first attempt if i really need RF > 250MHz, i will profile dso BW respond curve and compensate using manual calculator or my PC SW. for example if you know 400MHz is -2dB down, then you can calculate manually to add visible signal on screen with 2dB, more advance is using inverse FFT to compensate all spectrums and replot the signal on PC SW. i have suspicion that more advance GHz dsos do this kind of SW trick to get flat respond... ymmv.
Even with this sample rate it will still work. 800 MHz bandwidth makes possible to test signals up to ~80 MHz. 80 MHz square wave with 250 MHz bandwidth will be more like sinus and You lose precious data. Only one problem will be with spikes directly between two samples.
Speaking of bandwidth, I did one simple and stupid mistake...
Next time I should think more before doing simple job like that. Those two filters makes higher impedance at higher frequencies. so they added this capacitor. When I leaved it (with removed LC filters after it), impedance went down and signal was distorted. Same problem will be with mentioned 400 MHz "hack", when You leave it or remove it.
First LC filter is around 280-300 MHz (they made higher bandwidth than specified because of elements tolerance and eventual complaints because somebody didnt calculate total system bandwidth when using passive probes). Second one is probably around 800 MHz to filter out high frequency noise. Speaking of noise, after correcting my mistake (removing this capacitor) noise went from 74 uV RMS (originally) up to ~145 uV. After some time it went up to 300-350 uV making it less usable. I have suspicious about used thermopads was splashed and it added capacitance like it was with mentioned capacitor (same noise level - probably caused by capacitive load of opamp). Later I will check this.
I used 1mm thick thermopads. After that it was little pressure into thermopad on FPGA and on CPU (rk3399) heatsink was touching about half of it - measured temp. was increased by ~10° beside most expensive thermopads (6 W/m⋅K) from a local shop. Those on input stages was splashed like a cake...
So I measured height difference between those spacers (is that correct english name of it?) with a caliper. At input stages those are longer by 1 mm. So I think input stages should have 0.5 mm and everything else should have 1.5 mm. Workaround is to use 1 mm and 2 mm, but with less size due to splashing it around and possibly creating capacitance...
That is probably the worst aluminium heatsink I ever seen. Thermal conductivity is comparable to a cheap plastic. I think there is a way to hack this problem. Cut it to leave part around input stages and ADC, and cut other and better one to put it into everything else - maybe after that, fan wont be needed or one small at very low speed. Of course this heatsink is also a shield, so maybe it should be cut up to ADC and maybe little bit more.
Power dissipation for RK3399 is 6.05 W. I dont know how much is for FPGA (provided spreadshit doesnt work with LibreOffice correctly) but I assume we need similar size of heatsink due to higher total thermal resistance.
I need to divide next photos into another post because of total size limits and better readability. If somebody wants more photos, I already have much more.