There's been speculation that the bottleneck is the FPGA but we don't know that for sure.
It all depends on what generates the clock. It might be fixed by hardware though.
The clocks are most likely generated inside the FPGA via a PLL, based on an external quartz. You could reconfigure the PLL
if you had access to the FPGA VHDL or Verilog code -- but that would most likely not give you a working, faster data processing.
The permissible maximum frequency will depend on the transit delays of the logic gates and routing delays of the connecting fabric; it depends on how the circuit in the FPGA is set up. If we assume that the Rigol engineers are neither dumb nor mean, they will be running the FPGA close to the maximum it can reliably achieve.
Ok, there is the possibility that they
are mean.
Maybe the DHO800/900 are deliberately throttled to keep the DHO1000 series well-differentiated. But still, I don't think you can realistically re-configure the clock without access to the FPGA sources.