Thanks. I tried looking at the 250 MHz clock but it has spread spectrum enabled so looks terrible (picture attached)! I will have to remove the chip, rework the BGA site (add a 5 mil trace to strap differently, fix up solder mask, reball the IC, reflow it back) to try without SSC.
My scope does have all the advanced jitter measurements options. I will read in on this too to see if I can use it to get finer details. One thing I'm unsure about is a spec in the PHY datasheet that says that if an external oscillator it used (optional via pin strap) it should have the below specs. It seems reasonable that, when using the internal oscillator (with external XTAL), the specs should be similar.
I have attached screenshots of the frequency and period jitter of the 40 MHz oscillator. This is after the 1.8V switched power supply was replaced by a quiet external P/S. The PHY also has a 1.1V switched voltage rail but the SA only showed a 5uV spur at the switching frequency so I doubt any phase noise is due to the 1.1V switching noise. I could try to put in an additional 1.1V external P/S...
Edit: One thing that confuses me is that the below specs state "Reference clock jitter 50 psec (absolute p-p)". Peak-peak jitter includes random jitter, which by nature is unbounded. Therefore, it seems impossible to meet a 50ps TJ requirement. My scope (see attached image) shows the total p-p jitter to be 272 ps. The Std Dev. value is under 50ps (33ps) so perhaps should be used? I find the terminology and various measures confusing. How to interpret the below oscillator specs and compare with what I see on my scope?
5.2 Clock Source Requirements
5.2.1 Clock Source Selection Guide
Reference clock jitter is an important parameter. Jitter on the reference clock will degrade both the
transmit eye and receiver jitter tolerance no matter how clean the rest of the PLL is, thereby impairing
system performance. Additionally, a particularly jittery reference clock may interfere with PLL lock
detection mechanism, forcing the Lock Detector to issue an Unlock signal. A good quality, low jitter
reference clock is required to achieve compliance with supported USB3.0 standards. For example,
USB3.0 specification requires the random jitter (RJ) component of either RX or TX to be 2.42 ps (random
phase jitter calculated after applying jitter transfer function - JTF). As the PLL typically has a number of
additional jitter components, the Reference Clock jitter must be considerably below the overall jitter
budget.
5.2.2 Oscillator
If an external clock source is used, XI should be tied to the clock source and XO should be left floating.
Table 5-1. Oscillator Specification
PARAMETER MIN TYP MAX UNITS CONDITION
Frequency tolerance ±50 ppm Operational temperature
Frequency stability ±50 ppm 1 year aging
Rise/Fall time 6 nsec 20% - 80%
Reference clock RJ with JTF (1 sigma)(1) (2) 0.8 psec
(1) Sigma value assuming Gaussian distribution
(2) After application of JTF
Copyright © 2010–2012, Texas Instruments Incorporated DESIGN GUIDELINES 29
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TUSB1310A
SLLSE32E –NOVEMBER 2010–REVISED JULY 2012
www.ti.comTable 5-1. Oscillator Specification (continued)
PARAMETER MIN TYP MAX UNITS CONDITION
Reference clock TJ with JTF (total p-p)(2) (3) 25 psec
Reference clock jitter 50 psec (absolute p-p)(4)
(3) Calculated as 14.1 x RJ + DJ
(4) Absolute phase jitter (p-p)
5.2.3 Crystal
Either a 20-MHz, 25-MHz, 30-MHz, or 40-MHz crystal can be selected. A parallel, 20-pF load crystal
should be used if a crystal source is used.
Table 5-2. Crystal Specification
PARAMETER MIN TYP MAX UNITS CONDITION
Frequency tolerance ±50 ppm Operational temperature
Frequency stability ±50 ppm 1 year aging
Load capacitance 12 20 24 pF
30 DESIGN GUIDELINES Copyright © 2010–2012, Texas Instruments Incorporated
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