FNIRSI-1013D "100MHz" tablet oscilloscope

[Russell2024UK]

Atlan Thank you all noted will sort on my 1013D later  ... My friend now has his RTC DS3231 module kit to fit ( Solder in ) within his 1013D so will pass on your calibration process to him too  .. Have a great weekend...

[Atlan]

Manual, still not finished, but at least something. verzia V3, time 6:25

[Felipe Lacerda]

1. Charge the oscilloscope
2. Turn it on for at least 5 minutes to warm up.
3. Start basic calibration
4. Calibrate the input dividers
5. Calibrate the dc offset (to the channel cursor, to the zero signal and to the zero measured value)
6. Make a backup of this data using the Loader program.

Following the steps strictly 

Attached are the images with the signal position with 2V offset and 0V offset.

Calibrated with 2V offset signal to center of display. Ok?
But note that the signal with 0V offset the cursor is not exactly in the center.
I thought this adjustment was to position the cursor in the center of the display. I was wrong, apparently.

Anyway, it's a great job already done, tanks a lot! 

[Atlan]

But note that the signal with 0V offset the cursor is not exactly in the center

Base calibration no fix it?
Try switch ac and back to dc mode no fix?

[Felipe Lacerda]

But note that the signal with 0V offset the cursor is not exactly in the center

Base calibration no fix it?
Try switch ac and back to dc mode no fix?

AC coupling, the centering is perfect! 
DC coupling this small displacement happens.

It is just a fine adjustment, nothing critical for use. 

[Russell2024UK]

Atlan Thank you for sharing your info  Manual, still not finished, but at least something. verzia V3, time 6:25

[luisprata]

Hi folks,

I've notice that new fnirsi model dpox180h has the same f1c100 and FPGA, but it´s capable of annouced 50.000k waveforms/sec ... Does anyone have plans to reverse engineer this model too?  How can achieve so high refreshing rates?

[pcprogrammer]

I've notice that new fnirsi model dpox180h has the same f1c100 and FPGA, but it´s capable of annouced 50.000k waveforms/sec ... Does anyone have plans to reverse engineer this model too?  How can achieve so high refreshing rates?

The most likely thing is that they lied about that too, just as in that the 1013D does 1GSa/s.

I for one have no plans on getting one, let alone reverse engineer it.

[Atlan]

PC: How does this command work in FPGA? scopesettings.channel1.averagecommand    = 0x24;
how is the FPGA programmed - it only takes 10 samples from the signal? according to the sampling frequency from command 0x0D THX

[Atlan]

v0.025n remove fpga command 0x28 and 0x3C, change triger level long mode, fix acq menu long-short switch

[Russell2024UK]

I have firmware V0.025n  installed, How should the Single Trigger work ? My Sample Rate greyed out !!!  may be an user error  Ps whats the new firmware V0.025n supplied us with ?

[luisprata]

I've notice that new fnirsi model dpox180h has the same f1c100 and FPGA, but it´s capable of annouced 50.000k waveforms/sec ... Does anyone have plans to reverse engineer this model too?  How can achieve so high refreshing rates?

The most likely thing is that they lied about that too, just as in that the 1013D does 1GSa/s.

I for one have no plans on getting one, let alone reverse engineer it.

I agree. I was just curious how to improve waveforms rate in the 1013d reverse code. And yes, just for fun. As a scope, 1013d is very bad, but once you guys rewrote the code and made it an open source, it's very exciting to be able to mod and learn with it. I dont´t know any other scope similar with open code.

By the way, very good job and thank you very much! 

[Atlan]

Changing control of sample freq and time per div. in single trigger mode v0.025o
Tapping above the central axis changes the sample freq and time per div. Tapping below the center axis only changes the time per div.

[Russell2024UK]

Atlan Thanks I have firmware V0.025o  installed, Single Trigger Sample rate works now a treat now thanks for a super fast update  

[ECJ]

Hello everybody! I'm new here and firstly I would like to thank pcprogrammer and Atlan for this open source alternative firmware! I'm an electronics technician and programmer, and one of my hobbies is developing projects with microcontrollers, so i can imagine how much work this was and how much dedication was involved.

For now, i would just like to report that my touchscreen stopped responding during tests in acq long mode (trigger mode auto) of version 0.025o. The only way to get it working again was to go back to version 0.025m.

[pcprogrammer]

PC: How does this command work in FPGA? scopesettings.channel1.averagecommand    = 0x24;
how is the FPGA programmed - it only takes 10 samples from the signal? according to the sampling frequency from command 0x0D THX

The way the commands 0x24, 0x25, 0x26 and 0x27 are implemented in the FPGA is that they read data directly from the ADC busses. 0x24 => ADC1_A, 0x25 => ADC1_B, 0x26 => ADC2_A, 0x27 => ADC2_B. The data read is what is clocked by the last ADC clock signal, which is indeed based on the sampling frequency set with command 0x0D.

The averaging, or filtering, has to be done in the software to get a somewhat stable reading, since there is no synchronization on the actual sampling. The reading might be in the middle of a data transition and be complete rubbish.

As stated before the FPGA design is just as bad as the coding of the original firmware.

[Atlan]

Hello everybody! I'm new here and firstly I would like to thank pcprogrammer and Atlan for this open source alternative firmware! I'm an electronics technician and programmer, and one of my hobbies is developing projects with microcontrollers, so i can imagine how much work this was and how much dedication was involved.

For now, i would just like to report that my touchscreen stopped responding during tests in acq long mode (trigger mode auto) of version 0.025o. The only way to get it working again was to go back to version 0.025m.

read red text. P.S. everything works

[Atlan]

PC: How does this command work in FPGA? scopesettings.channel1.averagecommand    = 0x24;
how is the FPGA programmed - it only takes 10 samples from the signal? according to the sampling frequency from command 0x0D THX

The way the commands 0x24, 0x25, 0x26 and 0x27 are implemented in the FPGA is that they read data directly from the ADC busses. 0x24 => ADC1_A, 0x25 => ADC1_B, 0x26 => ADC2_A, 0x27 => ADC2_B. The data read is what is clocked by the last ADC clock signal, which is indeed based on the sampling frequency set with command 0x0D.

The averaging, or filtering, has to be done in the software to get a somewhat stable reading, since there is no synchronization on the actual sampling. The reading might be in the middle of a data transition and be complete rubbish.

As stated before the FPGA design is just as bad as the coding of the original firmware.

It could not be finished so that the FPGA is better used in terms of memory, and some usable trigger.

[ECJ]

read red text. P.S. everything works

Sorry. I went back to firmware 0.025o and ended up discovering that the problem starts to occur whenever the sample rate is below 200KSa/s. At 100KSa/s some screen touch failures begin. At 20KSa/s the screen no longer responds, unless I touch it repeatedly very quickly! It's as if the processor was busy, opening only small periodic windows to read the touch.

[ECJ]

Sorry again… Now I saw that this only happens with “long memory”. I accidentally activated it.

[Russell2024UK]

Regards Calibration and Accuracy Across Voltage Ranges of the Fnirsi 1013D - Regarding alignment I am seeing where some views of the signal (such as voltage measurement or grid alignment as an AC  sine wave ) are not perfect while others are perfect alinement….. Could this likely related to the calibration process. We are calibrating from 100 mV/div to 5 V/div with only one voltage per division range. Could this be limiting the accuracy across the entire range of the oscilloscope. Ideally, for better accuracy, Could we calibrate at multiple points within each range. With More calibration points across ranges: If possible, introduce additional voltage steps during calibration within each division range (e.g., instead of calibrating just at one voltage per division, try adding intermediate voltages in each range). would this likely improve accuracy across all ranges, 

[Atlan]

There is only one calibration value for each input divider. It makes no sense to do more, since the input part of the oscilloscope has a noise of approximately 2 bits, mainly for 2 channel. There is no point in trying for anything more.
Cinan was creative  to use the FPGA pins for AD0 and AD1 which are important for low signals, the gate on which the clock signal is connected.... 

[Russell2024UK]

Thanks    The question needed to be answered so thank you for that . At least we know there is only one calibration per input .. Emm where the input signal is scaled by different input dividers (e.g., 1x, 10x) thought this may effect things . Sorry i don't understand fully hence my User question - ( Cinan was creative to use the FPGA pins for AD0 and AD1 which are important for low signals, the gate on which the clock signal is connected) .. Thank you again for a prompt reply & explanation  .

[Russell2024UK]

Whats this square for at the bottom of our 1013D  ?

[Russell2024UK]

wolferl1210    Oh Thanks