I converted it to multiples of 16.
PC, you don't have a table somewhere about what the sampling frequency is if the value 2000 is written into the fpga. In the long time base mode. I assume that it is possible to change the frequency in order to achieve more uniform sampling when changing from about 100ms to 50s
Within the FPGA there is a 32 bit counter to divide the clock down. The value set for the sampling frequency is used as the divider, but I need to consult my work to give the formula and the clock frequency. Will get back to you on this.
Edit: I looked at the verilog file
here.
There is a variable "sample_rate_divider" that is used to make the sample clock. It is set with the FPGA command 0x0D.
The main clock runs at 200MHz. When "sample_rate_divider" is 0 the 200MHz is divided by 2 and the sample clock is 100MHz. This is the clock signal for the ADC's and the sample memory. For the software it means a sampling rate of 200MSa/s.
When set to 1 the 200MHz is divided by 4 giving a sample clock of 50MHz. For 3 it means dividing by 8 giving 25MHz.
The sample clock is based on the formula: clk = 200MHz / ((sample_rate_divider + 1) * 2)
The sample rate is then: rate = clk * 2
This only applies for when both ADC's are used to get the interleaved samples. When only reading data from one ADC the sample rate equals the clock rate.