Where did you get the information about the bus width? I tried to find info on the DRAM controller settings, but failed. Used source code from the sunxi factory for it but it does not provide a lot of insight in the working of it all.
Not sure actually. I think I saw that in a chinese forum.
Anyways, I made some benchmarks, stopping the TCON, so it doesn't used bandwidth.
CPU set to to 768MHz to reduce possible bottlenecks.
8GB memory copy:
dd if=/dev/zero of=/dev/null bs=1M count=8192
312MHz: 29.91s, 273.88MB/s
408MHz: 23.15s, 353.86MB/s
The performance increase is linear, so clearly the bottleneck here is the ram itself.
Being memory copy (read+write), the bandwidth would be 2x those numbers: 548 and 707MB/s
At 312MHz and 16bit bus, the theorical speed would be 624MB/s.
At 408MHz, 816MB/s.
The actual speeds are pretty close! Both benchmarks use 86-88%, with the performance drop caused by the timing signals overhead.