It is the difference of the clock rate of the DSO, and ofcourse related to the sample rate,
and the input frequency.
I would say that "the frequency of drifting depends on relation between input frequency and sampling clock", where the total jitter (in both sample clock and input signal as well) is responsible for the maximum drift amplitude. The minimum drift amplitude (well, that's the maximal resolution) is defined by the sampling rate.
Sorry, man, I don't think you're correct.
i can only recommend the R&S article to undertsand the difference between analog and digital trigger.
http://www.ecnmag.com/articles/2011/07/oscilloscope-performance-digital-triggeringhttp://www.rohde-schwarz.de/file/Benefits_of_RTO_digital_trigger_system_2.pdfCompare your delayed trigger picture to the typical analog trigger jitter picture in the pdf, they look very similar.
I know that Rigol said "DS2000 have digital trigger", the question is how
they implemented it.
Maybe someone can check this: the LMH6518 aux outputs, they routed somewhere. I think they routed to FPGA (the one over the ADC), i think to lvds inputs and their complementary inputs (of the FPGA) are routed to the DAC/MUX. That would be for analog or mixed trigger (levels analog, patterns digital). For pure digital (the implementation described by R&S) there should be no single signal path, however lmh6518 aux is for sure routed somewhere (but that didnt means anything, it can be used as well for hardware frequency counter).
So i can only repeat : we .. talking about ... the jitter added by trigger circuit, signal paths, FPGA design and potential firmware implementation. We don't know if Siglent have delayed trigger and how they measured, we don't know if they using exact the same design as Rigol, we know the FPGA are similar - but that only one less error source, we don't know exact used pins (which is as well good jitter source), we don't know hw they design looks like, we have no idea how rigol implemented the delay trigger (simply imagine the FPGA jitter x amount of delay elements and you will destroy any adavntage of digital triggering).
So i would say, check the aux routing, send Rigol nice email then with link to R&S pdf and ask them again about their trigger implementation.
For me this looks like analog level/digital pattern trigger and delayed trigger implementation with no errors (the smallest jitter amplitude is equal to sample rate, so that's ok - but as well proof of analog triggering). But maybe i'm wrong, maybe Rigol simply screewed up delay line and maybe they do have pure digital trigger and simply forgot to advertise that in DS2000 datasheet