Holly cow, you go to sleep a bit depressed and you wake up with a lot of cool activity
@fremen67 Vive la France !!! finally data, sweet data, to analyze
!!! Than you so much !!!
Now some comments:
Basic architecture:
- Having -PWRGOOD and -FPGARDY signals are a good and logic design decision, I did the same as @rhb and started the FP with the data connector out, it now explains why it blocks waiting for the two signals to drop, for the sake of experiment I will try to artificially pull them down and see how the FP display looks like, especially what waveform data is selected by default and how the picture of it looks.
- Having an address/data selector pin it's a bit meh, if the registers are always 32bits, it will introduce a minor complication while writing the new firmware, I'm curious how they switch in between reading and writing a register from the FPGA pov, because this will help us to produce the first and most important new firmware routines: register read and write.
- Detaching the actual configuration commands from the stuff that displays the waveform on the LCD, that IMO is the bulk of the transfers and should consist mostly of reads (sample the waveform description in FPGA to do a drawing ?!?!?), because for the non-FP firmware, we don't need to bother with little miserable pictures for starters.
Current data sets:
@fremen67
- I want to kindly ask you to do an 100MHz sampling "reference" capture for the initialization sequence, the SPI clock it's 18MHz and Shannon may wink from where it is
, so activate the RLE and buffering and get the full initialization seq for reference, I'll have to munch on it, it's a lot of research, for example I'm really curious if the FP reads the data from the SPI Flash first and then push it to the FPGA.
About the On/Off captures and the multiple train of pulses, this sounds a bit weird, I did my captures with CH1 already in the OFF state and counting the pulses for the push to ON, and even if my little LA it's outclassed by the diarrhea of data, it was counting reliably the number of transfers (NCSS going down), putting one transfer more in the trigger settings was not triggering it,
If you can repeat (again as 100MHz sampling) the measurement with the CH1 already in OFF state before starting measurement I will double grateful.
Logic Analyzer:
I've found this excellent Artix boards with lots of RAM and Cypress FX3 interface, and a digital designer to help me, the seller send the schematics and SDK and it actually looks sane, I'll try to produce an updated DSPro+ thingie to not be caught off-guard if the next project with an 33MHz SPI clock
. The analog front end will be a pleasure to design
. I'll let you know if you're interested, PM me, it's off-topic on this thread.
See you all in the evening,
DC1MC