Hello again, after a short nap to rest these old eyes, here are some quick answers to the messages until now and some new findings, aka "level control is a new level of...":
@cybermaus: Thanks for clarifying the RDP situation with the FP MCU, I downloaded the code form the Fraunhoffer project, once I have the protocol figured out (in case the firmware/FP dies at least I can control the SB via something else). I wish you'll find some time to contribute further to our little project, but thanks again for all your previous work, it was an inspiration.
@rhb: Your offer to do a detailed and formal protocol testing is wonderful, we need this and we desperately need at least one person with another AWG to do some investigation, as far as I was able to see until now, there are no "secret sauce" calibration values stored somewhere, the firmware trusts the SB to do its stuff, for example, I didn't see so far any difference in setting the amplitude for the channels in the actual firmware, but with your help we can really devise a calibration procedure for the device. Also thanks for the advanced debugger package info, it will come handy later. Finally, I will continue this thread for a while and tomorrow I will start a new one as suggested.
@SMB784: I will offer some of my findings to kick start your stuff, some are fact(F) and some are anecdotal (A, personal experience):
- F: As the SPI interface clock is 18MHz, you need an LA that can work reliably at least 100MHz in sample mode.
- F: The absolute minimum number of channels is 3: CS, CLK and MISO or MOSI, better is 4 (to see simultaneously both data pins) and best is 6, because we have some other signals (an assumed extra CS to select another device, and a "mystery" signal, not determined yet).
- F: The logic levels are 3V3, single ended, ALL the LA in the world should be able to cope with this.
- F: The LA has to have some on device memory, either large or with RLL or other compression method, we have some kind of trifecta thing, the data it's very fast when is coming, but come in widely spaced bursts, and a "naive" LA that once triggered, keeps on sampling, it will need to have a real large sample buffer.
- F: To add to the sample buffer size, I still have to see how the waveform loading goes over the SPI bus, it could be that my Intronix is insufficient for this.
- F: The LA should be able to have a reliable 16bit, MSBit first, protocol decoder, or it's useless.
- A: Personally I use an Intronix LogicPort (one right now on fleabay,
https://www.ebay.de/itm/INTRONIX-Logicport-34-Channel-Logic-Analyzer/192427289565 ), and they are still sold, while dated, it does the job (praise benevolent Fraser that offered one at a good price), it has RLL compression and some minuscule sample memory, so while the data can come as it wants, the few Kbits of sample buffer it fills up pretty fast and game over. Buuuut, if one is not lazy and expects the whole control msg in one shot, he can increase the number of trigger condition (CS going down) repetitions and position directly on the needed value or do a multi-segment acquisition. So far it proved to be OK, but I'm shopping for another LA, eventually with USB3 interface, and definitely with a large on device sample memory.
It's a tragedy that the Intronix guy got some kind of brain fart and totally refuses to update the design, he's a very pleasant and helpful person to talk with, UNTIL the design update subject comes
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- A: I was also looking at the DS Xilinx whatever clones, it doesn't seem to have RLL compression implemented, and if so, even with the 256KBits sample memory, it's useless. In streaming mode is definitely useless. But of course, I can only use the seller provided information, that is some distorted chinglish and on 10 similar looking devices you've got 10 different descriptions, they are throwing whatever shit and see which of it sticks on the wall and sells more. And most likely the software is nicely done and a pleasure to work with
.
I have lowered my LA standards as low as possible, but even so, finding a device that has the same features as the Intronix and a bit of extra buffer space under 1000EUR it's just not possible, Chinese or not. And btw, fuck those SA--äE sales drones with a rotating cactus, it took me half an hour with their miserable support software AI or cognitively challenged salesoid to confirm that the latest and grates expensive POS still doesn't have on device memory and doesn't do any RLL compression on acquisition and "it uses the PC memory". Sigh.
As this post has become too long, I will post the amplitude registers and description in my next post (that one will be also long, but with nuuuumeeeers
Cheers,
DC1MC
if it's one of these devices that are just some Cypress USB interfaces with some analog front end,