The interconnection between the soft FPGA (Xilinx XC6SLX16CSG324) and SOC (Samsung S3C2416 – 400 MHz) is a HS-SPI bus operating at 16.666667 MHz with three additional signals for FPGA code loading but should be able to operate on a faster HS-SPI data rate (up to 50 MHz as per the SOC specification), and the following enhancements can be added (usually without the need to reprogram the soft FPGA) but I am happy to provide a list of enhancements with FPGA reprogramming including waveform segmentation (different FPGA definition files can be reloaded without power cycling):
* Binary format for waveform file while retaining text-based header format with a “binary” type flag included.
* Address issue of slow loading of user waveforms (loading time increases exponentially every time the waveform size being loaded is doubled e.g. 1 minute for 250K points, 3 minutes 45 seconds for 500K points, 14 minutes 25 seconds for 1M points etc. - with the stock firmware, for each CPU-FPGA SPI bus cycle, a two-byte command is sent along with a maximum 128 byte payload.
* Manager for frequently used sets of instrument settings (waveform types, frequencies, amplitudes, offsets and phase degrees, sweep etc. with a short description field)
* FTP server (via USB Device or optional LAN)
* Remote FPGA code loading (code can be reloaded without power cycling)
* Remote firmware updating
* Front panel key reading and LED indicator control via USB
* Direct SPI bus control from the USB Device port while retaining original remote control commands