For an 8 bit ADC, a single pole filter would require an Fc 8 octaves below Nyquist. Sampling at 1 GSa/s to provide a 4 MHz BW DSO would not sell very well. So multipole filters are very necessary for a practical instrument.
Yet most practical DSOs do not have this! So how can they be practical?
Seismic processing is *very* obsessive about pulse shape. For marine work the boat goes out to deep water, drops of a buoy with a recorder and a hydrophone at sufficient depth below the surface. Not having been involved in that work, I don't know off the top of my head what "sufficient" is. As the the signature test, as it is called, is done in deep water there is only a single reflection at the sea surface to contend with. The boat makes a pass shooting and the response at small angles from vertical is recorded. The array of guns is designed to optimize the pulse shape around a narrow range of angles near vertical.
These are specialized applications operating at low frequencies where anti-aliasing filters in the linear analog, sampling analog, and digital domain are completely practical. An example of this are the
"better than Bessel" integrated filters made by Linear Technology. Increasing digital integration has made higher sampling rates and post acquisition DSP with minimal filtering in the analog domain the most economical way these days although it becomes very expensive albeit still viable at the highest bandwidths and sample rates which gets back to the subject of this discussion.
It used to be the case that one also applied a correction for the minimum phase response of the anti-alias filters and amplifiers in the AFE of the recording system. However, I would expect that correction is now applied in the recording system using an FPGA. The corrections are instrument specific and it is *very* hard to determine when boats made changes to their recording systems when reprocessing old data. And finding the instrument impulse tests is often impossible.
These corrections were also applied to analog oscilloscopes to correct things like dribble up in delay lines. With proper testing, you can actually see the result of this. These filters can generate preshoot in the transient response if the applied edge is fast enough which is rather disconcerting on an analog instrument. I have seen it on the Tektronix 2465 series oscilloscopes but *not* the older but slightly faster 7800 and 7900 instruments suggesting a design difference.
All the DSOs (6 OEMs) I've looked at apply a symmetric, zero phase interpolator. As a consequence, there is a precursor ripple that precedes a step. On some instruments you can avoid that by turning off the interpolator or switching to dot mode. However, some instruments always apply the interpolator even when in dot mode.
I have seen that before and concluded it was the Gibbs phenomenon. I did not have a fast enough pulse generator to test it on a Tektronix MDO5000 when I had a chance but the DSP bandwidth filters exhibited it and the hardware analog filters did not as expected.
As part of my FOSS DSO FW project I am examining the problem of the optimal anti-alias filter in detail. I am also examining the optimal interpolation filter. While it is commonly described as being sinc(t), that is actually not the proper operator. The proper operator is the minimum phase Fourier transform of the filter transfer function. It is a sinc(t) if and only if the filter is a zero phase boxcar. That's not physically realizable in a purely analog form.
It seems we have parallel DSO projects going. I am less worried about anti-aliasing and correcting the response in the digital domain because I want to make something more like an improved DPO style DSO where variable sample rate and variable depth histograms are created during decimation for essentially zero blind time. The objective is a real time index graded display which is completely faithful to an analog display but with complete digital measurement capability.
Performance of this design is completely dominated by memory bandwidth so large record lengths are useless because the memory never has time to be accessed. I would be ideal for an ASIC or FPGA using internal memory only.