DS1054Z possible problem with Sampling rate.

[JohnPen]

This may be a senior moment but I have just noticed that I can only get 1 GSa/s on channel 1.  With channel 1 switched Off the maximum sampling rate for individual operation of channels 2,3 and 4 is always 500MSa/s.  Normally I use channel 1 for most things and when adding a second channel, as expected, the sampling rate drops to 500 MSa/s.  Similarly adding a third channel drops the sampling rate to 250 MSa/s.     

NB: When running Self calibration initially all channels appear to be individually tested using the 1 GSa/s rate which implies any individual channel can be used at the 1 GSa/s rate.  Self Cal does complete successfully.  The F/W build is the latest Rigol version.  My scope is 3.5 years old.

So has it always been that way and I didn't notice or do I have an obscure problem?

[Fungus]

Yep, it's the trigger. I just checked.

This may be a senior moment but...

No, I did a double-take too. 

It's not obvious that  it can still be triggering on channel 1 even after you turn off the trace.

So has it always been that way and I didn't notice or do I have an obscure problem?

I hadn't noticed either.

[Yansi]

That is likely because it uses a software trigger and not a dedicated circuitry - which for a cheap osmelloscope should not be surprising.

[Fungus]

That is likely because it uses a software trigger

Is it still software if it's done by an FPGA?

and not a dedicated circuitry - which for a cheap osmelloscope should not be surprising.

Even with a dedicated analog trigger circuit you still have to resample/reconstruct the incoming data to cancel out the jitter (ie. all decent DSOs must do it ...)

[ogden]

That is likely because it uses a software trigger and not a dedicated circuitry - which for a cheap osmelloscope should not be surprising.

All modern DSO's uses waveform analysis for trigger. Ever heard of zone trigger? Even Keysight Infiniium Z-Series 63GHz BW, 160GSPS scopes. Do you call such "osmelloscope" as well?

[JohnPen]

Many thanks for the solution Peter it is all working as it should but a somewhat unexpected answer.   We live and learn.

John

Edit:  I have just found that if you set the trigger menu to AC all individually selected channels have the full 1 GSa/s sampling rate which actually makes sense.

[Paul Ed]

Thanks guys (especially @JohnPen @PeDre @Fungus ) as someone new to the DS1054Z recently, I've learned something, which is helpful.

[David Hess]

That is likely because it uses a software trigger

Is it still software if it's done by an FPGA?

Call it a digital trigger then.  The triggering occurs after digitization or after the ADC.

and not a dedicated circuitry - which for a cheap osmelloscope should not be surprising.

Even with a dedicated analog trigger circuit you still have to resample/reconstruct the incoming data to cancel out the jitter (ie. all decent DSOs must do it ...)

Reconstruction is necessary with a digital trigger because the trigger level is almost always between sample points.  This also implies that aliasing will screw up a digital trigger but I have not had an opportunity to test for this; the effect is probably small compared to other problems caused by aliasing.

An analog trigger includes a time delay counter which measures the time between the trigger and sample clock so no reconstruction to find this is necessary.  (1) Note that in most cases a digital trigger can do this reconstruction with the CPU *after* the acquisition to align the acquisition waveform with the display waveform.  But a DPO style oscilloscope has to do it immediately after digitizing before the acquisition record is stored.

(1) I do not know of any DSOs with analog triggers that implemented the time delay counter in software but it should be possible.

[rf-loop]

When talk is about digital trigger systems this R&S appno is very good to read.
Of course different manufacturers do things bit different way and also in cheap scopes may simplify something but main principles stay. Also this appno is quite old in this special thing because data handling brute force overall is gone fast forward and down in price.

R&S:Benefits of digital trigger system

There is also R&S paper what goes much more deep to inside  digital trigger... but at this time just now I did not find it

Of course there is fast interpolation between true sample points... how perfect it is depends...

About aliasing. Of course ADC aliasing may smudge everything. Decimated samplerate aliasing is bit different. How anybody can even think that system know what is alias and what is true if only knowledge is data out from ADC.
This is why manufacturers need take seriously filtering before ADC. There is NO free lunches. It need do and it need do carefully. Now many manufacturers, specially B and C brands are careless and lazy just in this very important point. They build many kind of digital filters after ADC and think all are happy. Yes it is easy and so on but only right place is in analog pathway before ADC. Period. 

Of course manufacturers can think that who cares if cheap scope is crap in this thing because users many time do not know anything but looks miracles and wonderful miraculous phenomena about electric signals on the screen and thats all. Siglent, Rigol, Hantek, Owon, whoever, / DO your homeworks and implement enough good filters to analog front end, even when some population may criticize this and are not happy because then they can not get amazing bandwidth. These are measuring and test equipments not entertainment systems or decorations. Many times best modification is reduce BW or modify front end BW shape to more steep and not try make it as wide as possible even when it looks like some kind of fashion when all want hack more MHz. More wide is not always best at all. ADC is frequency dowconverter...

If aliasing happen with decimated samplerate it may be different case with digital trigger engine because trigger can work before decimation always with ADC real running speed.

Digital trigger system have one obvious limit.

As the digital trigger uses the same digitized data as the acquisition unit it is important to note, that triggering only on signal events inside the ADC range is possible.

  Conventional analog trigger engine do not have this limit!

[ogden]

Digital trigger system have one obvious limit.

As the digital trigger uses the same digitized data as the acquisition unit it is important to note, that triggering only on signal events inside the ADC range is possible.

  Conventional analog trigger engine do not have this limit!

Thou you have option to dedicate another channel for trigger, use different volts/div and AC/DC coupling on it. This seems to match oldskool analog trigger capabilities (or not?)

[David Hess]

Digital trigger system have one obvious limit.

As the digital trigger uses the same digitized data as the acquisition unit it is important to note, that triggering only on signal events inside the ADC range is possible.

  Conventional analog trigger engine do not have this limit!

Thou you have option to dedicate another channel for trigger, use different volts/div and AC/DC coupling on it. This seems to match oldskool analog trigger capabilities (or not?)

I cannot say that I have ever encountered that problem on any oscilloscope, analog or digital.  More commonly I need more position range than a more sensitive volts/div will allow but that is what differential comparators are for.  It is difficult to argue with a position control that has 20,000 divisions of adjustment range.

In the past it was common for DSOs to only display a large fraction of the total DAC range leaving some range outside of the displayed signal for processing and triggering.  So for instance all except for my oldest Tektronix DSOs display 200 counts of the 256 count (8 bit) signal with the extra counts above and below the highest and lowest graticule line. (1)

There is a human factors engineering reason for this.  200 counts neatly divides by the screen resolution into 25 points per vertical division (2) so no aliasing between the acquisition and display records is created easing the processing requirements and producing a clear display for free.  The display resolution is 50 or 100 points per division.  The extra vertical resolution was used to more faithfully display the 16 bit display record when averaging was used.

A modern DSO could have enough processing power to antialias the display so this should not strictly be necessary but I do not think the result is as good and they all seem to cheap out on the processing for higher performance.  There is no benchmark that marketing can brag about for a faithful display.

(1) The displays are actually 1024 vertical so 12 display points, 3 acquisition record counts, are displayed above and below the top and bottom most graticule lines if you look very closely.  There is a similar "overscan" in the horizontal direction.  My oldest DSO lacks this because it displays 102.4 points horizontally and vertically for each graticule.

(2) 25 points is not universal.  I have seen 20 and 24 points used also.  My 10-bit scope uses 102.4 points.

[Fungus]

In the past it was common for DSOs to only display a large fraction of the total DAC range leaving some range outside of the displayed signal for processing and triggering.

The DS1054Z does this. Only 200 of the 256 ADC values are mapped to the screen, the rest are invisible above/below.

(but I think you can scroll them into view if you freeze the display and change the vertical position of a channel which was slightly off screen)