The bitstream is reprogrammed during update only, no load at each start. If the scope finds gsp file present in c:/bin at start, it programs it into PROM (there is a GPIO bitbang JTAG XSVF player), then deletes.
The BW bitfield of caps reg is 4 bits wide with possible values 1,2,4,8.
Other bitfields:
2 bits defining number of channels with possible values 1-2CH, 2-4CH
5 bits defining MSO capability and some yet unknown caps with possible values 0,1,2,4,8,16, 1 means "no MSO", rest are MSOs with some additional options, 16 defines some cool model with external serial keyboard instead of normal panel buttons.
It's unclear how FPGA itself samples those resistors - there can be something more than 0/1, like floating state detection, also possible values sets suggest "something to one-hot" decoding (it would look silly to sacrifice so many IO pins for direct one-hot strapping), so it's time for hw test.