Teardown : Agilent 16900A Logic Analyzer

[free_electron]

It's teardown time !
i've done this thing a couple of weeks ago: My new (used) 16900A Logic Analyser.
It comes from a reputable home (Worlds largest processor maker) where it was used to debug the frontside buses of the chipsets. Reason for dumping it... too slow 
Ah well.

This is it :

Little to see apart from the logo , software revision and a slot loading dvdrom drive.

Things change once you turn it around as that is the business end of this beast.


This is a modular instrument that can take up to 6 blades and be connected to an expansions chassis that can hold another 6 blades. Each blade is an acquisition board and different boards can be picked depending on what you need. There are even pattern generators to create signals.

Here is a picture of a 16750A blade installed in the chassis :


This is an overview of my older 16702B analyzer to give you an idea what a populated machine looks like
. Two of those blades will be transplanted to the new 16900A as they are compatible ( not all 700 series boards work in the 900 series.) when the transplant is done my 16900 will have three 16750A cards in it and 3 empty slots.

The bottom of the machine holds the computer tray. After removing 7 screws the two ejector latches let you remove the entire tray for easy access.


In it sits an 815 chipset based Pentium III mother board with 512 megs of ram that runs Windows XP. One PCI slot is used for a gigabit lan adapter card while the second one is ued for the Logic analyzer interface board. This machine doesn't really need a lot of horsepower computer wise. The software is well written and lightning fast. all heavy lifting is done by the analyzer blades and the PCI interface board.

The board at the bottom is the RIo interface ( Rapid I/O ). this taps into the backplane and picks off and feeds stimulus signals to the individual blades. it also feeds the RIO bus to the expander connectors to attach the other chassis. A couple of xilnx fpga's do the work there.


the PCI board connects the Pc's PCI bus to the backplane

The TI chip is a PCI master / repeater. it essentially takes an existing PCI66 slot and breaks it into multiple lanes. This chip has full PCI master capabilities. in other words : the chip can initiate DMA transfers directly into the working memory of the PC. any data that needs to be visualized is catapulted directly into ram by this beast. No need for software to futz around moving chunks of data...
The Chips (C&T) is an LCD controller. this is used if you buy the 16902A which has a built in touchscreen.
Two big Xilinx FPGA's complete the picture to translate the PCI bus into the RIO bus used on the backplane.

Agilent was smart enough to provide a power button both on the front and backside of the machine (the little 4 colro cable is another pushbutton with LED that is exaclty the same as the one on the frontpanel. Since this machine has no display it would mainly be installed with the back pointing at you so you can use the maximum reach of the probing cables.

A view of the backplane:

and a closeup of the area where the PCI interface board mates with the backplane:

there are various other FPGA's scattered throughout the board that go to connectors that are not in use in my machine. these are for other optional boards like tracing probes that can be installed.

All this silicon in the machine needs 'power'.. 1500 watts of it coming through big connectors from two honking switching power supplies.
.
Especially the analyzer boards are extremely power hungry.

A closeup of a blade :
.
Programmble comparators, level shifters, timing and trigger processors ( the heatsinked beasts ) , huge expensive FPGA's to do the memory interface and provide coprocessing for the data crunching and a wad of very fast ram. that's basically it. At a cost of 30K$ when this was new ...

The machine had been 'sanitized' when i got it . in other words the drive had been wiped. i installed a new harddisk , launched the recovery ( i have the master install DVD's ) , did all the windows updates as well as the software updates and the machine is back in perfect working order.
The other harddisk had been nuked ( both MFT's were gone, but the data is still intact ) but using a data recovery toolchain i was able to find the drive structure , extract the filetable and recover the licence files. This machine had some licence files for advanced triggering and bus decoding. So i was able to extract the file , plonk it on this install and it works perfectly fine. the licences are recognized and re-enabled.

You can hook up a VGA monitor , keyboard and mouse and drive it that way , or you simply connect the machine to your LAN , install the logic analyser software on any pc you have around and point it to the IP address of this machine. Agilent lets you run the analyser software on any pc you have around so you can crunch data without having the hardware. if you give the software the ip address of the real machine they handshake and you simply see the live data from this beast. The software supports multiple analyzers.

That's how i am going to run this thing. i installed the software on a fast Windows 7 machine and pointed it to this machines IP address. lightning fast.

[Zucca]

Can´t believe nobody respond to this, and I don´t care about the 120 days.

Thanks free_electron! Real nice job. Respect to the old LA!

PS: I just got a 16702b (your trusty old puppy)... I will soon post something on it.

[Psi]

Must have got buried in other threads at the time. I dont remember seeing it at all.

Awesome analyzer, it puts my saleae analyzer to shame

[Alex Eisenhut]

I like the free angle traces.

[georges80]

...
The Chips (C&T) is an LCD controller. this is used if you buy the 16902A which has a built in touchscreen.
...

Wow - I just saw the C&T chip and thought, hmm, zoom into the picture and verify the part number... 1995/1996 vintage.

I designed the fifo control logic (VHDL was the design language used at Chips) that sits between each of the modules (that run on different clock domains) inside that chip. Was a bit of a scary time since the control logic had synchronisers to deal with the fifo read/write logic to keep track of position/fullness and being asynchronous signals one has to worry about metastable states... Fortunately it all worked well

I also wrote the test bench for the PCI interface to the chip to simulate it on some big/expensive IKOS hardware simulation boxes that had been sitting in the company essentially unused until that point. Same test bench also worked with the VHDL software simulation environment we used.

When the first silicon came back it was flaky, I got the lucky job of ebeam probing it (we had an inhouse ebeam system). The assumption was that there was a bug in the PCI block (which I inherited due to my test bench expertise since the designer of the PCI block had left to go to S3 - remember S3?). Anyhow, after a bunch of probing (which really only worked on metal 1 I came to the conclusion that the layout group had screwed up the placement of the multiple parallel big buffers & routing of the main clock - they had let place&route deal with the clock block, twits! Anyhow finger pointing back & forth between design and layout and no scapegoat could be found. Fortunately they didn't shoot the messenger (me) and they re-spun the chip and all was good on the 2nd rev.

Fun times back then and something completely different given I'm a systems level engineer, not a logic designer.

Thanks for the flashback

cheers,
george.

[nctnico]

S3? Yes I remember it stood for Sh*t^3 !
Anyway, look at a teardown of a Tektronix TLA7AA4 acquisition module and the acquisition module above suddenly doesn't look that hot 

[free_electron]

...
The Chips (C&T) is an LCD controller. this is used if you buy the 16902A which has a built in touchscreen.
...

Wow - I just saw the C&T chip and thought, hmm, zoom into the picture and verify the part number... 1995/1996 vintage.

I designed the fifo control logic (VHDL was the design language used at Chips) that sits between each of the modules (that run on different clock domains) inside that chip. Was a bit of a scary time since the control logic had synchronisers to deal with the fifo read/write logic to keep track of position/fullness and being asynchronous signals one has to worry about metastable states... Fortunately it all worked well

I also wrote the test bench for the PCI interface to the chip to simulate it on some big/expensive IKOS hardware simulation boxes that had been sitting in the company essentially unused until that point. Same test bench also worked with the VHDL software simulation environment we used.

When the first silicon came back it was flaky, I got the lucky job of ebeam probing it (we had an inhouse ebeam system). The assumption was that there was a bug in the PCI block (which I inherited due to my test bench expertise since the designer of the PCI block had left to go to S3 - remember S3?). Anyhow, after a bunch of probing (which really only worked on metal 1 I came to the conclusion that the layout group had screwed up the placement of the multiple parallel big buffers & routing of the main clock - they had let place&route deal with the clock block, twits! Anyhow finger pointing back & forth between design and layout and no scapegoat could be found. Fortunately they didn't shoot the messenger (me) and they re-spun the chip and all was good on the 2nd rev.

Fun times back then and something completely different given I'm a systems level engineer, not a logic designer.

Thanks for the flashback

cheers,
george.

IKOs. that brings back memories. we also had the one that was later borged by cadence. exxentially a huge machine full of FPGA's. can;t remember the name.

[free_electron]

this review is now outdated. i got the 16902 ( with the touch screen ) and a couple of 900 family blades as well as the pattern generator for it.

i;ve been so busy lately that i haven;t had time to tinker with my goodies ...