The goal would be to have the data in linear planes so all ch1 data for a given acquisition would be in order, followed by ch2, ch3 and so on. I'm not too worried about where individual waveform groups are, but each channel should be in a separate plane. That way, when data is read out, it is in order (besides the need to rotate for pre-triggers.) In theory, I can then have another, say, 16-bit side channel for MSO functions, which is on ADC clock. (It would also be possible to do state analysis for MSO function using this, although it might be difficult to line that up with analog channels at that point.)
This is something I wanted to do a while ago, but the complexity put me off. But, I'm realising what a pain it is to have to deal with interlaced data when it comes to plotting data and processing it afterwards with filters and the like.
I think one of the biggest challenges to solve is memory arbitration, given one 64-bit AXI bus has 1.6GB/s peak bandwidth I'll need to appropriately arbitrate, possibly across two ports, to make this work well, to avoid running out of bandwidth as more time will be sent setting up smaller transactions.