Enclosed here is a visual of an LTSpice simulation of a FET-based soft-latching power switch circuit. I also include the LTSpice .asc file:
(I hope the graphic appears inline, but I digress).
As I am still a relative noob I have some questions about the TP2 output waveform. The overshoot may be o.k. depending on the nature of the switching regulation intended to be downstream from this circuit. The strange undershoot during the odd-numbered events on the Vsw pulse train plus the stuff going on that makes the waveform look like the south end of New Mexico to me.
Is this going to be acceptable to most of the buck converting devices around? The intent is for a 3.3V buck-regulated supply.
The other question for me is speculative. I am aware that the potential exists for problems with slow-discharging capacitive loads when switch bounce is occuring. The inrush current is likely to be excessive for the main supply (a lithium cell with only 900 mAh storage capacity. I am aware of another design involving a diode, cap, and resistor added to a similarly simple circuit, which would seem to convert the pass FET into some kind of comparator so the slew rate is low for slow-charging of downstream capacitive loads. For various reasons I am leery of diving into that bowl of gumbo when this circuit seems to be working well enough for resistive loads. Ideas? Other concerns?
J.R. Stoner from beautiful metropolitan Redding, CA (:-)