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Too bad that project is on hold.
Any decent designer
ought to have a handful of projects on hold!
I mean that, giving birth to an idea does not necessarily mean that spiritual inspiration can be switched ON and OFF on demand; there will always be lots of other variables in the way...
Thank you for your kind words!
Actually, speed is no concern since a lot of the time the firmware has to wait, e.g. for the ADC. There's also no gain from changing the crystal from 8 to 16 MHz; a faster ADC would help. A zero offset of the ADC was already discussed and the idea was dropped. A changing offset (=noise) helps with the oversampling.
Thank you for the information.
If I am not mistaken, I can see that you are
Markus, the author of the current
-m versions along with Karl-Heinz's
-k ones! Firstly, let me congratulate you both for your efforts.
I am familiar with oversampling and the decimation/averaging method of achieving higher resolutions as well as with the (random) noise injection method of a few LSBs into the under test signal, in order to assist oversampling. I also agree in that the standard 8-bit AVR ADC might be insufficient for any faster or any better accuracy results than those already achieved, since its non-linearity and gain errors put a ceiling to the final acquisition product maximum resolution accuracy.
Now, it is a fact that even 1 LSB offset error narrows down the usable range of the 1024 discrete steps of the 10-bit ADC available output by one unit, affecting the final product value by introducing a minor scaling error. Is this the reason why the ADC results offset corrections were overruled? Because, during the auto-calibration procedure, the offset error can be measured, compensated, and it can be used for the calculation of the usable ADC range; and all these additional ADC parameters can be also stored in EEPROM along with the other device parameters.
A complete correction of the ADC linearity and errors using our PWM voltage source would be interesting. That would need some great assembler coding for speed. It would probably at best double the accuracy but the hardware cost would be a few caps, resistors and another test connection to output the PWM. And time.
I really like your idea, Richard!
Changing dynamically the voltage reference by the use of the available PWM hardware might breathe new life into this already impressive project, by expanding dramatically the device's dynamic range. Of course, any fancy hardware changes will be a problem to the existing standard devices, which will not be able to make use of any possible new features without any PCB/hardware (heavy) modifications.
Other than that, and based on the latest Component Tester schematics, any of the PC5:PC3 spare I/O lines could be exchanged with PB1 (or PB2) in order to take advantage of the OC1A (or the OC1B)
16-bit PWM outputs (with a sub-millivolt resolution!); another ADC line of the spare ones (PC6:PC3) is needed to be driven by the configurable PWM voltage reference generated (through an additional RC low-pass filter). The external crystal should not be dropped (in order to utilise the PB7:PB6 I/O lines) because it would impair the time-based measurements accuracy. The only drawback I can see is the additional time needed (in the order of a couple of hundreds of milliseconds) for the PWM output RC filter to reach its final output before it can be used as a stable voltage reference. As a bonus, the very low level ripple induced by the PWM stage will assist oversampling.
Unfortunately, the m168/m328 ADC does not support differential channels input, nor the relatively high impedance PWM stage RC filter output can drive directly the 32 Kohm AREF input line without any external buffering; but this error can be measured and compensated if this configuration is chosen to be used.
In a few words, the improvements potential of this project seems to be promising! I guess that I will have to build a device (or order a chineese copycat) for any further experimentation...
-George