Si5351a gitter free quadrature clock signal generation?

[Tharkun]

I believe with some jiggery pokery, it is possible to generate two gitter free clock signals locked in quadrature using the Si5351a.  Hoping someone has the code and Si5351a config to do this.  I believe this is the best way to generate the clock signals to drive the multiplexer of a Tayloe detector Rather than use 2 D flip flops.

Can anyone help?

Cheers,

Tim

[radiolistener]

yes, it's possible. The best way is to generate x2 frequency for two output and activate inversion flag for the one of the channel. Then use external low jitter divider IC to get quadrature.

Also you can generate quadrature with using phase register, but si5351 phase control resolution is not good, so it will be not precise and don't recommended if you're needs a good quadrature. Also the min frequency is limited to about 2-3 MHz for a phase control register method.

[fourfathom]

yes, it's possible. The best way is to generate x2 frequency for two output and activate inversion flag for the one of the channel. Then use external low jitter divider IC to get quadrature.

Also you can generate quadrature with using phase register, but si5351 phase control resolution is not good, so it will be not precise and don't recommended if you're needs a good quadrature. Also the min frequency is limited to about 2-3 MHz for a phase control register method.

The Si5351 phase control resolution has limited resolution, but is quite precise.  With the proper output divider and phase control (delay) divider values you can get an extremely accurate quadrature output.  To get fine control of the frequency you then adjust the PLL frequency.  Yes, the lower frequency limit for this setup is around 3 MHz, and if I recall correctly the upper limit is VCO/8, or around 112 MHz.
Here's a link to a good presentation of this technique: https://qrp-labs.com/images/news/dayton2018/fdim2018.pdf  See page 14.

To get frequencies lower than 3 MHz with the 5351 one technique is to set up two outputs with frequencies perhaps 1/10th or 1/100th Hz difference, wait the correct amount of time (that allows the two clocks to shift into quadrature), then change the divider so the frequencies are equal.  This seems a bit "iffy", but it apparently works well: (Google translate link) https://cibxpwpxhlmaa52pa52rbd5wcy-ac4c6men2g7xr2a-tj-lab-org.translate.goog/2020/08/27/si5351%e5%8d%98%e4%bd%93%e3%81%a73mhz%e4%bb%a5%e4%b8%8b%e3%81%ae%e7%9b%b4%e4%ba%a4%e4%bf%a1%e5%8f%b7%e3%82%92%e5%87%ba%e5%8a%9b%e3%81%99%e3%82%8b/

[radiolistener]

The Si5351 phase control resolution has limited resolution, but is quite precise.  With the proper output divider and phase control (delay) divider values you can get an extremely accurate quadrature output.

As I remember, the phase control register has just 0...127 value range. In order to get 90 degree phase shift, phase control register should be loaded with multisynth divider value. It means that multisynth divider needs to be integer value within 0...127 range. Otherwise you will get phase error for a quadrature output.

Since it's hard to keep multisynth divider as an integer value within limited range 0...127, the proper phase shift will be available for a very limited frequencies.

The much better way is to use external IC to divide outputs by 2 and setup twice higher frequency on the CLK0 and CLK1 with enabled inversion flag for CLK1 output (and don't forgot to feed both channels from the same PLL). It allows to keep clean quadrature and precise phase shift for any frequency.

[fourfathom]

Since it's hard to keep multisynth divider as an integer value within limited range 0...127, the proper phase shift will be available for a very limited frequencies.

But it's *not* difficult to keep the multisynth divider as an integer value within limited range 0...127 (actually the even numbers from 4 to 126).  The VCO has a range from 600 MHz to 900 MHz, with excellent resolution in the feedback dividers.  This means you can get gap-free quadrature output from 225 MHz down to 4.76 MHz. In practice the VCO has a wider range than 600-900. giving more range on the quadrature output frequency if you dare.  By adjusting the PLL feedback dividers you can tune the output frequency over a 66.6% range without needing to reset the output dividers.

[jan48]

You can GOOGLE   "jason milldrum si5351 library"    for arduino code

[radiolistener]

But it's *not* difficult to keep the multisynth divider as an integer value within limited range 0...127 (actually the even numbers from 4 to 126).  The VCO has a range from 600 MHz to 900 MHz, with excellent resolution in the feedback dividers.

Hm, you're right, with a fractional multiplier for PLL we can get almost any frequency with integer 4...127 divider for multisynth. And it can be used for quadrature. In such case the min frequency will be 600/127 = 4.72 MHz. I was used a little different approach. Needs to test this one.

[fourfathom]

But it's *not* difficult to keep the multisynth divider as an integer value within limited range 0...127 (actually the even numbers from 4 to 126).  The VCO has a range from 600 MHz to 900 MHz, with excellent resolution in the feedback dividers.

Hm, you're right, with a fractional multiplier for PLL we can get almost any frequency with integer 4...127 divider for multisynth. And it can be used for quadrature. In such case the min frequency will be 600/127 = 4.72 MHz. I was used a little different approach. Needs to test this one.

I was using 600/126 = 4.761906 MHz, since we need to use an even-integer output divider. 

But what happens with an odd divisor?  I'm not sure, but I suppose the asymmetry of the resulting output waveform will cause quadrature jitter?  The Si5351 has an output "de-jitter" block that filters the would-be jittering outputs, presumably using a tapped delay line or similar, but I don't know how this affects delay-register quadrature mode.  The de-jitter filter does works quite well to clean up the output spectrum -- the typical spurs you would normally see with a plain clock-dropping fractional divider are really cleaned up in the '5351.  Not perfect, but much better.

[Bud]

Right, it should be a question to the application designers what their phase noise requirements are, which not all can answer because they have no idea what phase noise is in the first place...

[Tharkun]

You are right I can’t define phase noise mathematically. My requirements are for a quadrature clocks with as little as possible gitter between each as is possible with the Si5351a.  I’m driving a multiplexer that samples an rf signal to generate I and Q signals for demodulation of an ssb signal  by phase shift either with op amps or with audio dsp in a microcontroller.  All I know is maintaining accurate phase shift between the clocks is all important as inaccuracies will effect the quality of the demodulated signal and unwanted side band suppression.  Usually 2 d flip flops are driven at a frequency 4 times higher than the required clock to generate the required, but I believe this isn’t perfect, and better results can be achieved by running 2 clocks from the si5351a and phase adjusting 1 with respect to the other. 

Looking at the Si5351 documentation, this is an involved process, that doesn’t appear to be covered in the standard libraries available for the si5351a, though it has been solved by Hans Summers of QRP labs.  Don’t believe he’s keen to provide his code.  He does explain what he did in a presentation, referenced in this thread, but it’s involved…. Oh well looks like I’ll have to dive in myself and try to work it out.

[radiolistener]

Looking at the Si5351 documentation, this is an involved process, that doesn’t appear to be covered in the standard libraries available for the si5351a, though it has been solved by Hans Summers of QRP labs.  Don’t believe he’s keen to provide his code.  He does explain what he did in a presentation, referenced in this thread, but it’s involved…. Oh well looks like I’ll have to dive in myself and try to work it out.

For 90 degree shift it's easy, just load phase control register with the divider value used for multisynth. Since phase control register is integer and has limited range 0...127, you're needs to use multisynth divider with the same limitations - integer with range 0..127, otherwise phase shift between I and Q will not be exactly 90 degree.

As I remember, phase control register is applied on PLL reset, so it may needs to perform PLL reset.

[richard.cs]

Usually 2 d flip flops are driven at a frequency 4 times higher than the required clock to generate the required, but I believe this isn’t perfect, and better results can be achieved by running 2 clocks from the si5351a and phase adjusting 1 with respect to the other.

I'm not really convinced that the flip flop approach would have inferior performance.

FYI you usually use two flip flops, an inverter and 2*f input provided the input duty cycle is known to be 50% (if it's not it manifests as phase error), but using 4*f allows you to put a third flipflop as divide-2 up front to fix any duty cycle errors. With a 3-flip-flop approach you become independent of your clock duty cycle, and you eliminate the inverter as you can use the complementary outputs. Your phase error is then set by the skew in the inverters and can be very low if you use a suitably fast logic family.

[fourfathom]

Usually 2 d flip flops are driven at a frequency 4 times higher than the required clock to generate the required, but I believe this isn’t perfect, and better results can be achieved by running 2 clocks from the si5351a and phase adjusting 1 with respect to the other.

I'm not really convinced that the flip flop approach would have inferior performance.

FYI you usually use two flip flops, an inverter and 2*f input provided the input duty cycle is known to be 50% (if it's not it manifests as phase error), but using 4*f allows you to put a third flipflop as divide-2 up front to fix any duty cycle errors. With a 3-flip-flop approach you become independent of your clock duty cycle, and you eliminate the inverter as you can use the complementary outputs. Your phase error is then set by the skew in the inverters and can be very low if you use a suitably fast logic family.

Yes, but the skew in the Si5351 is also very low.  The chip uses a process that gives them a 900 MHz PLL (and I've run them well over 1 GHz in testing) so it's got that going for it.  I read somewhere that some guy did some measurements and the 5351 had lower skew than his discrete quadrature FF implementation.  But take that for whatever it's worth, as I don't even remember what discrete logic family he was using.

I wish I had a faster scope!  I was considering one of the old Tek sampling scopes on ebay, but couldn't make myself click the "BUY" button.  I do have a MiniCircuits phase detector I should put on a test fixture so I can measure 5351 quadrature phase jitter.  Perhaps I will get around to it...

[UR5FFR]

Hi

Try my library for Si5351 https://github.com/andrey-belokon/UR5FFR_Si5351. It allow generate quadrature output also.
But you cannot generate a quadrature below 4 MHz because it requires the VCO to operate at less than 600 MHz, it may become unstable. Therefore, the library does not guarantee operation in the range from 2 to 4 MHz - this may depend on your copy of the SI5351.