What gain is the AD8138 configured for? With a high enough gain, one would expect to see the thermal noise power of the 50-ohm termination rise above the quantization noise floor.
It is configured for unity gain, both R
F and R
G = 510 Ω.
V
OCM is connected to ADC VREF pin.
Could you post what you're using for the 96 MHz sampling clock? If it's a packaged oscillator, it is likely a third or fifth overtone type, so one would expect subharmonics. If you can, measure the sampling clock on a spectrum analyzer.
I'm using Chinese TCXO in a DIP package with no datasheet
Yes, it looks that it has subharmonics oscillator inside and have some spurs, but it looks that it has better phase noise than other oscillators that I have at the moment, because when I use it I see not so much spike of noise floor around carrier from a clean carrier feeding at ADC input, other oscillators that I have are much worse than this one). Unfortunately I cannot measure it on a spectrum analyzer and there is no way to buy a new oscillator or other components, because there is a very difficult situation...
50 kHz is a common SMPS frequency, could be leakage through a power line.
Yes, probably it can be related to power lines for ADC. When I touch it, I see some change in these unwanted noise. But I can't figure out what's going on, because these changes are not reproducible and hard to predict. ADC has a capacitors and ferrite bead on power line near the chip, but probably this is not enough. Needs to experiment with better power line filtering.
I'm using Chinese linear lab power supply which powers two
LT3042 based regulators to produce two separate 5V power, one for ADC and second for oscillator (through additional 3V LDO with capacitors and ferrite bead on oscillator board).
May be I have noise vulnerability in the power scheme, because there is 20 cm wires between power regulator and ADC board. When I touch these wires, I definitely see some changes of unwanted noise.
Finally, what's the cause of the strong DC component? Is there a bias voltage being applied? Or is that just the offset voltage from the opamp?
I think this is offset voltage from opamp. Zero voltage on opamp input leads to a some offset on the ADC output. When I test it, I found that I need to apply a little offset voltage on the input in order to use full scale.
I know that transformer provides better performance, and I have transformer for replacement. But it needs to desolder opamp for testing. At the moment I need ability to see low frequencies near DC for debugging, so that voltage offset is not an issue for me.
I'm not sure, may be that low frequency noise can be related with negative power line which is connected to the ground (for unipolar power mode). But it is connected to the ground on the power regulator side and there is about 20 cm of wires. I found a little voltage drop on a ground power wire, because ADC consumes about 270 mA. So actually opamp negative power line has a very small negative voltage which may depends on the current consumption of ADC. And another possible issue that I see is that 3 power lines can catch some noise from environment due to ground loops.
I tried to power opamp in bipolar mode and didn't get noticeable change, so I decided to return back to unipolar power mode which is more convenient.
Here is waterfall with a low frequency noise around DC component. Pay no attention to the RMS level, because it is shown for IF stream after DDC and LPF, I just added a little more attenuation for a FIR filter to avoid overflow for a full scale DC.