Fastest soic8 fet driver

[stretchyman]

Hi ALL.

My current project is a class E HF A.M. transmitter and am trying to get the switching frequency above 15MHz.

Have been using 6nC GaN FET O/P devices and NCP81074 drivers without too much trouble, altho' drivers do get a bit toasty!

My new goal is 20MHz with 10nC (approx 1nF Ctot) GaN (Nexperia TO247's) and am looking into the plethora of SOIC drivers as there are many to choose from and wonder (hope) that someone out there may have found the fastest one available?

Specs vary with rise times quoted from different manufactures into varying loads (1nf, 1.8nF, 10nF) with no chart as to rise times vs gate charge, so not easy to compare.

Other than being SOIC8 it will have to have a solderable pad on the underside, some of the smaller packages use this already but SOIC8 is very easy to use for me as it's not too small.

I'm thinking of trying ISL89163FBEAZ as it's looks good but rise time is slow compared to NCP81074 but this is into 10nF vs 1.8nF for the NCP driver.

Anyone, any thoughts?

Btw the drivers must be SOIC8 and I've already used much lower Qg FETs (4nC DFN8) but the TO247s make it easier to build and service.

Your help and advice would be much appreciated!

Best Regards

Stretchy.

p.s. had posted on another board but figure this is a more appropriate one.

[mtwieg]

I've never used a GaN-optimized gate driver which wasn't in a leadless package (DFN, SON, BGA, etc), but after digging around a bit it looks like there are some options in SOIC and SOT packages, mainly from TI. At a glance, LM5114, UCC27511A, UCC27524A, and UCC27624 are worth considering.

Speaking from lots of previous experience, once you go much beyond 10MHz it's impractical to get clean rectangular waveforms into the gate of any FET, unless you use very specialized devices (no leaded packages) with a tight layout. If you are really determined to stick with SOIC and TO-247, I would suggest doing a resonant gate driver, in which case the gate waveform will be roughly sinusoidal. This approach works very well with class E amplifiers (so long as they are properly tuned).

[MarkT]

For very fast GaN I'd look first to the manufacturer's evaluation kits which have driver and FET integrated with very low inductance layout - hard to replicate that yourself, and low inductance is crucial to faster operation.  I've used the EPC2903 board in the past (obsolete now though), which was 11x12mm with two GaNFETs and driver (i.e. a half-bridge) integrated into a surface-mountable PCB module...

[stretchyman]

Appreciate the reply as didn't seem to attract much interest!

I need way more than 100V tho' as class E runs at 3.5 X Vcc and usually use a safety factor of X3 so 500V+ assuming I use 50Vds.

Cheers.

JB

[temperance]

10nC @ 20 MHz, assuming Vcc is 12 V (which is probably not correct to drive the GaN device)

P_drive= Vcc x Qg x f
P_drive= 12 V x 10 nC x 20 MHz
P_drive= 2.4 W

Enough power to prepare a very small toast on top of the SO8 package. Some heatinking will be required. An SO8 might not be the best choice considering the solution will be larger when taking the extra heat sink into account.

[stretchyman]

Yes indeed, 10nC being about right for the Nexperia GaNs.
I've used bigger driver packages but there's an issue with keeping the input/output connections short.

Just wondering if anyone out there has tried different drivers to find the fastest?

You can use 6V for GaN, so half the power required.

Thanks for the reply.

[mtwieg]

I need way more than 100V tho' as class E runs at 3.5 X Vcc and usually use a safety factor of X3 so 500V+ assuming I use 50Vds.

Eh, that amount of margin is pretty excessive IMO. A breakdown voltage six times the drain bias voltage should be sufficient. You might be better reducing the bias voltage to 15-32V, which opens up a lot more options for device selection, then step the output voltage up with a transformer.

If you really want the most power out of your devices, I would consider using a push-pull topology like current mode class D (CMCD).

Just wondering if anyone out there has tried different drivers to find the fastest?

Respectfully, those looking to push frequency so high generally don't constrain themselves to SOIC and TO packages...

[temperance]

Just wondering if anyone out there has tried different drivers to find the fastest?

I don't know how you are approaching this. Are you looking at some specified rise and fall times in data sheets or calculating the real rise and fall times for each FET and driver combination?

If you're looking at data sheet numbers it is important to look at the test conditions.

[stretchyman]

Thanks for the reply.

Trying to generate 500W with 15V isn't going to work!

50V is an absolute minimum and like to use as its 'safe'.

Not sure what you mean by 'bias voltage'? Drain voltage maybe?

I am using CMCD and push pull class E, voltages are still x3, that and most of the go to GaN and SiC devices are 900V+

 To answer the other reply ...

I am approaching it by already having a working design and  trying to increase the frequency whilst trying to keep efficiencies north of 85% and having sharp turn on and off times and cool(ish)drivers.

Im thinking as PCBs cost virtually nothing these days that I may be best to lay out the 3 (found so far) different pinouts and just drive 1nF and check the waveforms.

Cheers Both.

J.

[temperance]

I am approaching it by already having a working design and  trying to increase the frequency whilst trying to keep efficiencies north of 85% and having sharp turn on and off times and cool(ish)drivers.

I think this will help you to calculate the gate drive requirements:
https://archive.org/details/bitsavers_siliconixdixMOSPOWERApplications_38092918/page/n111/mode/2up

Chapter 3.2, switching Characteristics

[stretchyman]

Hi thanks for the reply.

My browser wont load the link (security issue) so will try another.

Im aware of how to calculate the drive power however.

Still looking for someone who has practical experience of this rather than theoretical..

Cheers.

J.

[mtwieg]

Trying to generate 500W with 15V isn't going to work!

50V is an absolute minimum and like to use as its 'safe'.

It definitely can, with proper device selection. Though I'd probably pick a max drain bias between 30-40V, and use 200V rated FETs.

If this is for an AM transmitter, I assume you'll be modulating amplitude via envelope tracking on the drain bias voltage, probably with a stepdown DCDC. I'd use 48V as the supply to the envelope tracking DCDC, and set it up so its output voltage (the bias on the RFPA stage) is 30-40V.

Not sure what you mean by 'bias voltage'? Drain voltage maybe?

Correct.

I am using CMCD and push pull class E, voltages are still x3

Right, even with ideal half-sine waveforms the peak drain voltage will be the drain bias voltage * pi. In my experience it ends up being around Vbias*3.5. 

that and most of the go to GaN and SiC devices are 900V+

I'm guessing you have this impression because you're only considering devices in through hole packages. But there are plenty of GaN devices rated 40-200V (though not in through hole packages, for good reason). EPC is the most prominent in that space, but GaN systems have some 100V devices and I think Nexperia has some too.

Im thinking as PCBs cost virtually nothing these days that I may be best to lay out the 3 (found so far) different pinouts and just drive 1nF and check the waveforms.

Sounds reasonable, let us know what you find!