Hello. I am attempting to send a packet using the Silicon Labs Si4332.
While the receiver appears to receive the packet, and gives me the correct packet length,
the content of the packet is wrong. It consist of the last byte of the packet, repeated for the entire length.
On both the transmitter and receiver I set the following registers
Reg 0x71 = 0x23; // GFSK modulation, FIFO as data source
Reg 0x05 = 0x06; // Packet sent, packet received interrupt
Reg 0x75 = 0x53; // 434 MHz
Reg 0x76 = 0x64; // 434 MHz
Reg 0x77 = 0x00; // 434 MHz
On the transmitter I do:
Reg 0x08 = 0x01; // Clear TX Fifo
Reg 0x08 = 0x00; // Clear TX Fifo
Reg 0x3e = 0x04; // Data Length
Reg 0x7F = 0x31 0x32 0x33 0x34 // Data
Reg 0x07 = 0x08; // Start TX
On the receiver I do:
Reg 0x08 = 0x02; // Clear RX Fifo
Reg 0x08 = 0x00; // Clear RX Fifo
Reg 0x07 = 0x04; // Start RX
Wait for packet received bit (0x02) in Reg 0x03
Received size = Reg 0x48
Receive data from Fifo 0x7F
Result: Received data is 0x34 0x34 0x34 0x34
These examples in code
https://github.com/a-v-s/ucdev/blob/master/demos/radio/si433x/radio_test.c Does anyone have any idea what I am doing wrong?