How to create an FPGA-controller local oscillator?

[technix]

This is for my own SDR project, which uses the main FPGA and its attached TCXO to generate all the clocks. Now I need something to convert the FPGA clock outputs from its internal PLL to something useable by the RF-IF mixers. How?

[radar_macgyver]

This clock topology is not recommended from a phase noise perspective, since typical FPGA clock synthesizers are not optimized for low phase noise; also the clock signals can pick up a lot of noise from other logic on the die. I would recommend using a dedicated clock synthesis chip with a clock output tree, and use one of it's outputs to clock the FPGA, other outputs to the mixers.

To get a clock off the FPGA, maybe configure an FPGA I/O as LVPECL or LVDS, and use a balun to convert to single-ended (ensuring that the FPGA I/O has appropriate termination). The balun will reject some of the common-mode noise introduced by the FPGA's power and ground being shared with other logic signals.

[Berni]

Analog Devices makes a whole range of chips for this very task:
https://www.analog.com/en/products/rf-microwave/direct-digital-synthesis.html

Just get the chip for your particular frequency range and feature set and connect it to the FPGA via SPI. Some of them will also do modulation on the output waveform by sending it high speed IQ data over parallel or LVDS.

The benefit of these chips is also that they have a DAC inside that creates a sinewave output, so much less filtering is needed to turn it into a nice clean spectraly pure tone.

[radiolistener]

This is for my own SDR project, which uses the main FPGA and its attached TCXO to generate all the clocks. Now I need something to convert the FPGA clock outputs from its internal PLL to something useable by the RF-IF mixers. How?

FPGA has very bad jitter performance. It is bad for SDR. The better way is to feed analog circuits directly from a low phase noise oscillator through low jitter buffer. And feed the same oscillator through second buffer to FPGA clock input.

Typical SDR DDC usage is to feed ADC directly from a low phase noise oscillator and then feed ADC output to FPGA and using output OTR/READY pin of ADC as a clock for FPGA. All processing should be done in ADC clock domain and then transferred to PHY (Ethernet or USB) clock domain through FIFO buffer.

But there is possible issue with OTR/READY clock timing. It may be not 50% duty cycle and it may cause timing issues in your FPGA design, so I recommend to design PCB layout to feed oscillator output through separate low jitter buffers to analog circuits and to FPGA clock input. In such case both clocks will be available for FPGA (original oscillator clock and ADC output clock). And you can debug and investigate issues.

Also I don't recommend to use TCXO. They have a spurs and jitter around carrier. It's better to use VCXO. If you're want to get precise frequency you can use Vcontrol pin for fine tuning. It can be easy implemented with frequency reference comparison. Just divide VCXO and reference sources to get the same frequency and XOR them, then use analog low pass filter and feed Vcontrol pin of VCXO for fine tuning. You can use some precise TCXO, rubidium standard or GPS disciplined oscillator as a reference source for VCXO fine tuning.