Tuning PCB end-launch transitions

[jmw]

I'm trying to understand how one goes about systematically tuning the transition from an end-launch connector to a PCB transmission line. A lot of times the pin and solder pad are wider than a 50 ohm trace, so it's recommended to taper or step the trace width and remove a little bit of ground plane at the transition to compensate for the extra capacitance. In my case, I'm using layer 3 on OSHPark's 4-layer stackup as ground to get a wider trace that matches the size of the connector pin. I'm using openEMS as a field solver to try out ideas, and my target frequency range is below 3 GHz, since that's all I can measure with my current equipment. First thing I did was dial in the trace width and gap for a grounded coplanar waveguide.

So far the things I've found:
1. with no transition (ground and trace all the way to the board edge) I get around a fairly flat 33 dB of return loss into an ideal termination on the PCB. Not too bad really
2. Remove layer 3 ground plane at the transition: very little change
3. Stepping coplanar ground gap at the transition: introduces a resonance that can improve the return loss over a targeted range but doesn't really change the worst case

The connector I'm using (https://www.digikey.com/en/products/detail/142-0701-801/J502-ND/35280) is cheap and doesn't step down the coax size, so I think that is a limiting factor. There's a lot of room for fields to spread at the end.

All of this has been trial and error. Are there any other things I should try with this launch setup?

[jmw]

Best result with the stepped coplanar ground:

[KE5FX]

Sounds like you have your answer...?  You're not going to beat 30 dB of return loss in the real world with this class of connector, nor is there any reason to try.

[Hamelec]

imho: 15 dB of return loss is "good enough", more is "nice to have" or academic.. 

[jmw]

Sounds like you have your answer...?  You're not going to beat 30 dB of return loss in the real world with this class of connector, nor is there any reason to try.

Hah, fair response. I wasn't sure what counts as "good enough" in the lab. If 15 dB of return loss is acceptable for calling it done, then it makes sense.

[Hamelec]

Depending on your lab 
I am talking for HAM purpose..

[Weston]

Forgive me if you have already seen this, but here is a really cool project on GitHub where someone is using OpenEMS to model a SMA > microstrip transition

https://github.com/toammann/Multilayer_SMA2Microstrip

For the SMA pin the impedance will be too low, so it's really just a matter of iterating through and simulating/verifying possible cutout geometries. Having a scripted pipeline to parameterize the edge launch is a big help in doing that.

[KE5FX]

That's a nicely-documented effort.  OpenEMS needs (and deserves) more publicity, for sure.

[jmw]

That Github page was actually the inspiration to simulate the transition with this other connector, but it doesn't explain how he settled on the final geometry. I found a paper about using openEMS with a custom excitation to simulate TDR (https://cdn.hackaday.io/files/1656277086185568/gaussian_step_v11.pdf). It seems you could use the result to see which parts of the transition are mismatched and then adjust the geometry.

[eleguy]

Great work!

I tend to use more old fashioned      method every time the material changes. In practice, one has to design and order a test board (see pic). Usually solder "blob" has also some influence to the results. Would there be a way to simulate that? So far these super basic(?) sma connectors have been fine in the frequency range we are working. Manufacturer claims big numbers but due the instruments we have I can test things only until 6GHz. Certainly cheap-ish JLC06161H-3313 material is not the best but has potential in the mixed signal applications and it works fine with some care.

[eleguy]

https://github.com/toammann/Multilayer_SMA2Microstrip

Should have read until this far before posting anything from solder "blobs". In this example solder mask has been used in a clever way to prevent solder messing up the transmission line. Thanks for the link!

[jmw]

I added some extra metal (not visible looking straight down) in the simulation to have a wider connection between the pin and trace. You could also add a more realistic looking solder fillet. I think the effect of a solder blob in practice might have to do with how close to the board edge the solder has wicked under the pin.

[Weston]

That Github page was actually the inspiration to simulate the transition with this other connector, but it doesn't explain how he settled on the final geometry. I found a paper about using openEMS with a custom excitation to simulate TDR (https://cdn.hackaday.io/files/1656277086185568/gaussian_step_v11.pdf). It seems you could use the result to see which parts of the transition are mismatched and then adjust the geometry.

You actually dont need to change the excitation waveform to generate TDR data. It is possible to calculate the TDR response directly from S parameters. Here is an example using the python skrf library: https://scikit-rf.readthedocs.io/en/latest/examples/networktheory/Time%20domain%20reflectometry%2C%20measurement%20vs%20simulation.html

In terms of what metal to remove, the idea is to find where to add cutouts that normalize the impedance but do not themselves add resonances at higher frequencies and maintain the highest frequency cutoff for propogation modes other than the desired TEM mode. In abstract, this is not too useful, but there are probably papers on it. And you can piecewise analyze the cutoff frequencies of any structures. I suspect that a lot of this is just done by brute force iterating through and simulating what looks reasonable.

[Marsupilami]

As with a lot of other things the METAS VNA Data Explorer can be great help with this task too.
On the main screen you have the possibility to look at time domain representation of your s-parameter data. Moreover in a separate dialog it can also do time gating.
The only two gotchas are that 1. it doesn't convert to normalized impedance, it only displays reflection coefficient. Second the frequency spacing has to be so that the first frequency equals the frequency step. (E.g. 10MHz, 20MHz, 30MHz...,)

As an example here's a via I just worked on:

You can see the interations as I adjusted the features. Started from black, ended up at green.
The two peaks at 60 and 100ps are the two outer layer pads, while in between, esp at the peak at 85ps you can see the coax like barrel of the via. (The board is ~2mm thick)
From here it is iterative, looking at which sections seem more capacitive or inductive and adding or removing copper accordingly.

Another useful trick for this method is that you can often simulate your structure to significantly higher frequencies than what it could do in real life. The highest frequency in your freq domain data determines the time resolution after it's converted, thus a wider freq sweep will result is improved spatial resolution.  Above example was simulated to 60GHz.

With all that said for the longest time I've been looking for good literature on this topic. I've seen industry veterans use the weirdest of conductor shapes and I'd be very interested in a good, half theoretical / half practical guide about those. If any of you have tips please share.