NanoVNA Custom Software

[ogden]

That doesn't mean that the acquisitions are synchronized so that the same part of each IF cycle is sampled.   How many clocks of the crystal on the SI5351A correspond to the RF and LO signals and the MCLK driving the codec and the microcontroller?  They are all on separate fractional dividers.

Many commercial VNA's have multiple Fractional-N synthesizers as well. For example N5222 have three independent synths (RF LO, source1, source2). Only difference to NanoVNA - ADC clock of "commercial VNA" usually is not PLL-synthesized. BTW MCU&ADC of NanoVNA also can be clocked from "jitter-less clock", directly from XTAL (thru mode of SI5351A). Just knowing that any PLL have phase errors is not enough. Did you actually analyze impact of SI5351A phase noise on measurements?

[profdc9]

If you put the IF on a scope, you can clearly see the jitter.  I don't have a spectrum analyzer to measure the phase noise in dBc/Hz but a zero-crossing detector clearly shows the edge of the pulse moving around.  If you have two high frequencies with very close fractional divider settings, as you would have when the difference between the RF and LO is a IF frequency a thousand times smaller or more, their mixing product will not repeat until the counters for both fractional dividers both run through their counts and realign.  A fractional divider guarantees that a fixed number of pulses of approximately the same length are produced per time interval, but some are pulses stretched a VCO cycle and others are not depending on the state of the fractional divider counter.  This means it might take many milliseconds with a 20-bit fractional divider for the output clock signal to repeat.  There will be beats between the two signals that will reoccur over the millisecond repeat intervals of the fractional divider counter of the two signals, which means the edge of the mixing product of the two clocks can move around on a time scale over milliseconds.  Depending on the state of the fractional divider counters when you start and end sampling, the phase of the signal may or not may not be what the microcontroller expects the signal to be and uses to demodulate the signal.   Some way for the microcontroller to know the phase of the IF signal, such as a zero-crossing detector or other trigger signal, could be helpful in ensuring repeatable measurements.  A fast XOR gate would be ideal for this purpose, or a zero-crossing comparator triggering off of the reference.

[ogden]

No need to seek for instruments or build them because you already got one - VNA itself. Just run thru calibration at single frequency for some time to gather "statistically enough" phase/magnitude readings. Phase spread bell curve (if any) will indicate phase measurement accuracy.

[DH1AKF_Wolfgang]

Please imagine, how this VNA works:
There are three mixers, all driven with the same frequencies f1 and f2.
IF = f2-f1 is constant.
All phase jitters in the IF are the same.
In addition, low-pass filters and  especially the FFT include calculations and give further average values. Your considerations of phase jitter do not lead to a meaningful result.

And keep in mind: This is a product for ham radio enthusiasts, not intended for professional use.
For antenna matching/measurement it is fully sufficient, also for tuning a filter or amplifier.

[ogden]

Please imagine, how this VNA works:
There are three mixers, all driven with the same frequencies f1 and f2.
IF = f2-f1 is constant.
All phase jitters in the IF are the same.

Incorrect. f1 and f2 are coming each from separate Fractional-N synthesizer (PLL-A & PLL-B), their jitter definitely are not the same.

[joeqsmith]

a product for ham radio enthusiasts, not intended for professional use.
For antenna matching/measurement it is fully sufficient, also for tuning a filter or amplifier.

My friend who gave me one wouldn't have any idea what amateur radio is, and I have no interest in it.   That certainly doesn't mean that we have no use for the Nano.  I would imagine any hobbyist experimenting with high speed designs that has never used a VNA could benefit from it.  As a minimum, it may help cement some  concepts.   IMO, it's a great product for anyone wanting to learn the basics.   

[DH1AKF_Wolfgang]

>> Incorrect. f1 and f2 are coming each from separate Fractional-N synthesizer (PLL-A & PLL-B), their jitter definitely are not the same.<<

Hello, Ogden, you misunderstood me.
My statement refers to the difference f1 - f2.
And to the averaging of the FFT.

[ogden]

>> Incorrect. f1 and f2 are coming each from separate Fractional-N synthesizer (PLL-A & PLL-B), their jitter definitely are not the same.<<

Hello, Ogden, you misunderstood me.
My statement refers to the difference f1 - f2.
And to the averaging of the FFT.

Please explain what you mean by saying "All phase jitters in the IF are the same", how there can be more than one jitter in the f1 - f2 difference. Are you sure you fully understand PLL synths?

[profdc9]

Ok, it looks like I opened up the can of worms in Pandora's box, or whatever mixed metaphor you like.

I am going to try to put an example forward.  Say the PLL VCO is 600 MHz, and we want the RF signal to be 10.25 MHz and the LO to be 10.26 MHz.  The integer divider for both the RF and LO signal is 58.  The fractional part for RF=10.25 MHz is 0.53658 and for the LO=10.26 MHz it is 0.47953.   The divided by 58 frequency is 10.34482 MHz and the divided by 59 frequency is 10.16949 MHz.  So we expect the RF signal to actually be at a frequency of 10.34482 MHz for 0.46342 of the time and 10.16949 for 0.53658 of the time.  Likewise, the LO frequency is at 10.34482 MHz for 0.52047 of the time and 10.16949 MHz for 0.47953 of the time.  While some of the pulses have a period of 96.7 ns, and others 98.3 ns, they must be interleaved so that the instantaneous IF beat frequency between RF and LO does not deviate too much.  I am not sure how the SI5351A actually interleaves the two sets of divided pulses, perhaps it uses a sigma-delta modulator?  Nevertheless, one can clearly see the period of the IF vary on the scope.  For a 3.333 kHz IF frequency (3rd harmonic) I see about 2-4 microseconds of jitter.  For a 300 microsecond period, that corresponds to 3 microseconds = 3.6 degrees or 0.0628 radians, which suggests an instantaneous frequency variation between 3.300 and 3.367 kHz, but it averages to 3.333 kHz.  Because the SNR of a single measurement is approximately 1/(radians) that would be a SNR of about 16 or 12 dB.  But if we integrate over many cycles, we can improve this by assuming the phase errors are independent.  Of course they aren't, and if you integrate assuming the correct third harmonic mean frequency (10 kHz) when you demodulate the phase errors ought to cancel out and the signal improvement should be better than assuming independent phase errors.  But if the instantaneous frequency of the IF is varying a little bit due to the fractional divider, say 1% or so, that does contribute some phase error to the demodulated signal.

I tried to deal with this problem by actually clocking the ADC using a zero-crossing detector.  However, there are probably better ways, or maybe the integration time is long enough in practice that this error source is negligible.  But it is not true that the period of the IF is constant but it does average out over a long interval.

[Bud]

I posted some linearity and error magnitude calculations on the list where I concluded you must stay 20dB below IP3 and 10dB below P1dB to get reasonable EVM.

So much trouble to investigate something that has been known for ages, seriously ...?   

[OwO]

Apparently not by the original developers of the Nano which drives the mixers close to P1dB.

[OwO]

Above 140MHz on the V2 the si5351 is unused and there are no fractional dividers on the RF path or ADC clock path. The MCU and ADC are NOT clocked by the si5351. They are driven by a clock buffer that is sourced directly from the TCXO. The si5351 has lots of spurs on its output but the phase error only becomes noticeable above 200MHz, so we switch to the ADF4350 as low as possible.

[ogden]

I am going to try to put an example forward.  Say the PLL VCO is 600 MHz, and we want the RF signal to be 10.25 MHz and the LO to be 10.26 MHz.  The integer divider for both the RF and LO signal is 58.  The fractional part for RF=10.25 MHz is 0.53658 and for the LO=10.26 MHz it is 0.47953.   The divided by 58 frequency is 10.34482 MHz and the divided by 59 frequency is 10.16949 MHz.  So we expect the RF signal to actually be at a frequency of 10.34482 MHz for 0.46342 of the time and 10.16949 for 0.53658 of the time.  Likewise, the LO frequency is at 10.34482 MHz for 0.52047 of the time and 10.16949 MHz for 0.47953 of the time.  While some of the pulses have a period of 96.7 ns, and others 98.3 ns, they must be interleaved so that the instantaneous IF beat frequency between RF and LO does not deviate too much.  I am not sure how the SI5351A actually interleaves the two sets of divided pulses, perhaps it uses a sigma-delta modulator? 

Your whole "explanation" is fundamentally wrong from very beginning where you assume that both VCO's are tuned to exact same frequency out of specified 600..900MHz range. Granularity of Fractional-N synth frequency steps is good enough to avoid fractional ratios of output divider meaning everything you just explained do not apply. Hopefully OwO can elaborate here.

[ogden]

The MCU and ADC are NOT clocked by the si5351. They are driven by a clock buffer that is sourced directly from the TCXO.

Don't you use internal PLL of MCU? - STM32 have inherent clocking architecture flaw - when ARM/bus clock source is PLL (which indeed have phase noise), you can't clock ADC directly from XTAL. Dunno about GD.

[OwO]

Yes, the ADC is clocked from the internal PLL. It's integer N, and probably has no good phase noise, but in our tests it was still found that the ADF435x phase noise dominated (you can see an almost linear increase of phase noise floor as RF frequency is increased; ADC sampling jitter would be independent of RF and LO frequency changes).

Above 100MHz the si5351 operates with a fixed output divider of 6. Below 100MHz the fractional divider is indeed used and it's done this way to get more frequency precision. My original code actually tried to use the same output divider for RF and LO, while mainly using the multiplier (feedback divider) to set frequency, but this resulted in slower lock times and slow sweep rates.

However, there is speculation that the si5351 fractional dividers aren't just dumb ones that switch between N and N+1, but also has a programmable delay network to correct the output edge timing. I'm not sure if this is true (and the datasheet doesn't talk about it), but I'm inclined to believe it based on the observed spur floor. I've used chips with a dumb fractional divider before and they produced far higher spurs.
See: https://groups.io/g/BITX20/message/29001

[OwO]

There are a lot of differences in the RF and DSP design between the V2 (S-A-A) and the original Nano, because S-A-A is not actually based on the Nano. S-A-A was designed before the Nano hit the market, and we already had all the basic VNA infrastructure. The timeline is like this:
- Early 2019 - S-A-A-1 was designed as a 1-200MHz antenna analyzer using a si5351, no LCD and only USB interface, to retail for $20.
- May 2019 - NanoVNA began selling on taobao, but the news hasn't yet gotten to us
- Aug 2019 - NanoVNA becomes popular outside of China, and I first hear about it. I immediately inform our client and hold a meeting about direction.
- Sept 2019 - It is decided that S-A-A must go up to 3GHz to compete. The design rework starts and we make a decision to integrate the NanoVNA's UI.
- Dec 25 2019 - Design work meets spec at iteration 2 (the third iteration). Firmware and software are also in usable shape.
- Jan 2020 - We submit final designs to client and give the green light to manufacturing. Software and firmware work continues.

The S-A-A-2 started off as a separate project unrelated to the Nano, but we have integrated the UI from the Nano (and fixed a shitload of bugs). Unfortunately I can't upstream these bugfixes because the refractoring included a port to C++17, switching all code to use std::complex, and quite a bit of rework of the UI event handling and drawing code. Of the bugfixes there were stack corruptions, drawing bugs, basic math (geometry) errors (which caused the persistent old traces on screen) etc.

[ogden]

Above 100MHz the si5351 operates with a fixed output divider of 6. Below 100MHz the fractional divider is indeed used and it's done this way to get more frequency precision.

I see. That's because you match IF frequency precisely. IMHO performance of MCU is good enough to calculate sincos coefficients on the fly (using cordic), thus relaxing IF frequency precision requirements so you can use integer dividers for < 100MHz as well. Just saying.

[profdc9]

Regardless of the source of the jitter of the SI5351A, and unless an engineer from Silicon Labs is going to chime in here, you might want to do the measurement I did and see how much the IF period varies before you decide it's not a problem.  By triggering the acquisition off the zero-crossing and sampling at four times IF, I can get away with four Fourier coefficients: 1, j, -1, -j and so all of the quadrature demodulation can be performed using additions and subtractions.  No guessing at the phase relationship of various PLLs both internal or external to the microcontroller.  And by synchronizing, I can integrate a smaller signal with a small IF bandwidth so I don't have to greatly overdrive the SA612 to obtain enough signal, even though the acquisition takes longer.  It's the same principle used for a lock-in amplifier which is able to accumulate signals with a very low SNR.

I am not sure any of the people who use the NanoVNA care about this, or care about the accuracy of their instrument, because for $50 they will like whatever they get.  I wanted to put together something that used as many commodity parts as possible so that it does not become obsoleted like so many other antenna analyzers or VNAs in the past, be easily built without excessively small SMD parts so that hobbyists with limited skills could reproduce it if it can not be obtained commercially, and be completely and unquestionably open source hardware and software so that others could continue to change and improve it even if I can not.  Unlike the Chinese vendors, I have to worry about legal repercussions if I don't respect the copyrights of others, and edy555 seems to not be too happy about where the NanoVNA is going.  I am not going to make money off of the VNA I designed, I just want to point out a problem I found that could be a concern for others designs that could be improved, as in the end I think the main interest is getting good equipment into the hands of hams.

[ogden]

Regardless of the source of the jitter of the SI5351A, and unless an engineer from Silicon Labs is going to chime in here, you might want to do the measurement I did and see how much the IF period varies before you decide it's not a problem. By triggering the acquisition off the zero-crossing and sampling at four times IF, I can get away with four Fourier coefficients: 1, j, -1, -j and so all of the quadrature demodulation can be performed using additions and subtractions.

Are you sure about your measurement? I am asking because specified jitter of SI5351 is <100 ps (picoseconds). What scope did you use? BTW phase noise measurements of SI5351 are looking surprisingly good: https://nt7s.com/2014/11/si5351a-investigations-part-7/

[OwO]

Regardless of the source of the jitter of the SI5351A, and unless an engineer from Silicon Labs is going to chime in here, you might want to do the measurement I did and see how much the IF period varies before you decide it's not a problem.  By triggering the acquisition off the zero-crossing and sampling at four times IF, I can get away with four Fourier coefficients: 1, j, -1, -j and so all of the quadrature demodulation can be performed using additions and subtractions.  No guessing at the phase relationship of various PLLs both internal or external to the microcontroller.  And by synchronizing, I can integrate a smaller signal with a small IF bandwidth so I don't have to greatly overdrive the SA612 to obtain enough signal, even though the acquisition takes longer.  It's the same principle used for a lock-in amplifier which is able to accumulate signals with a very low SNR.

I get the use of 4*IF sample rate, but I don't get what you are talking about with the phase relationship. As I said, the VNA detects phase difference between the reflected and a reference signal, so no guessing at phase relationships anywhere.

Adding a zero crossing detector and aligning the ADC sample clock edges with the IF period boundaries will do nothing, because the IF signal is the product of two high frequency carriers and its phase is completely arbitrary; for example just the microstrip trace between the coupler output and mixer input will alter the IF phase, and this phase shift is based on the phase change of the RF carrier so is highly sensitive to distance.

Also IF bandwidth is inversely proportional to the integration time. This is a fundamental fact of physics regardless of how you do the IF detection. The optimal detection is simply multiplying with the complex sinusoid (as you are doing), plus integrate and dump. As I'm aware the Nano also does this.

[OwO]

I've also verified that the measurement noise floor when using the si5351 is not noticeably higher than the ADF4350, and see no change in noise floor below 100MHz when the fractional dividers are active. I'm not sure if you can even measure jitter with an ordinary scope, but I've looked at the raw baseband signal from the ADC using GNU radio and didn't see higher noise floor with the si5351 fractional divider. Plus at these low frequencies other noise sources dominate anyway, which is likely why I don't see a change when switching from si5351 to ADF4350. Once you get to 1GHz however, the phase noise floor is clearly visible in spectrum view and it's on-par with what the ADF4350 datasheet says (plus a few dB due to noise folding).

[profdc9]

Put the IF signal on a scope and see for yourself.  Even a modest oscilloscope can do this.  That is what your codec/microcontroller ADC sees.  You don't have to take my word for it.

[ogden]

Apparently not by the original developers of the Nano which drives the mixers close to P1dB.

What you guys think - is there any chance to improve performance of original Nano as it is? Lowering input levels of ref & reflected mixers is kinda easy (1 & 2 resistors), reducing OSC level for all mixers piece of cake, but then what? Most likely IF level will decrease and codec gain (or rather lack of it) will be problem, right? Basically we trade linearity for dynamic range, right? Or not?

Put the IF signal on a scope and see for yourself.  Even a modest oscilloscope can do this.  That is what your codec/microcontroller ADC sees.  You don't have to take my word for it.

Nah. Multiple sources - jitter specs, phase noise figures, use of si5351a in many HAM DIY HF receivers do not agree with what you say.

[joeqsmith]

Member enut11 posted about making their own attenuators.  I decided to show a few examples using the Nano compared with my other old network analyzers.  At the lower frequencies, the numbers the Nano throws up is pretty decent.   For these tests, things start falling apart once we get beyond 0.3GHz or so.  Still, it's impressive for $50.       

https://www.eevblog.com/forum/projects/20db-rf-attenuator-seeking-feedback-to-improve/

For the fun of it, I soldered an unknown 51.6MHz crystal to a test board as a shunt to look at the reflection coefficient.  This was the highest part I had on hand and I would suspect is a 3rd overtone.    It was swept from 10MHz to 55MHz with a 0.1MHz step (45,000 data points) to see if there were any other areas where the device would react. 

One of the problems with my old 8754A VNA is without using an external generator, looking at narrow band signals like this can be a problem.   The frequency is low enough that my 3589A can display it. 

[joeqsmith]

I had shown an attempt to make a low cost transfer relay for the nano.   One of the things I had did to show how poor its performance was along with the nano was to run a T check on it.  On the left is a screen shot from that video showing +/-20% up to 500MHz.   On the right, using these same home made "standards" on a better system, sweeping to 900MHz.

I had made a really cheep power supply made from a 4000 CMOS part to drive my old transfer relay from the USB adapter.  The transfer relay is latching, so the power supply just charges a large cap that I then dump to the relay. 

Working on putting together some better standards for my hobby use.   
https://www.eevblog.com/forum/rf-microwave/get-ideal-networks-from-cal-kit-parameters/msg2921098/#msg2921098