NanoVNA Custom Software

[joeqsmith]

Showing the new transformer and CAT5E test cable.

[joeqsmith]

I had posted how my friend Shimp's LiteVNA was very noisy and how I have made up a dropping USB cable to improve it.   I have been using Dislords unreleased firmware that he posted here that improved the AGC (V1.2.09).   Today I tried out the latest firmware 220228 and at least the AGC is still working.   My plan is to transition over to the new firmware (assuming I don't run into any problems with it).   

This VNA would get much worse (noise) when the battery was removed.   I ended up pulling the 220uF bulk and adding several tant and ceramics to try and improve the noise.   Shown even without the USB dropping cable, this VNA is now as low as my other VNA.  Removing the battery now has no effect.   

[joeqsmith]

I had also attempted to bump up the IF gain a small amount.  The noise was too high and my first attempt yielded no improvement.    I made another attempt and saw a slight improvement.

[joeqsmith]

New release is now available.  I made a short clip showing how to use the new TDR memory feature.

[joeqsmith]

Scratch pad reminders....

https://www.salukitec.com/resource/time-domain-reflection-tdr-impedance-test/

https://scdn.rohde-schwarz.com/ur/pws/dl_downloads/pdm/cl_manuals/user_manual/1173_9163_01/ZNB_ZNBT_UserManual_en_62.pdf

https://www.signalintegrityjournal.com/articles/432-s-parameters-signal-integrity-analysis-in-the-blink-of-an-eye
***
http://teledynelecroy.github.io/SignalIntegrity/SignalIntegrity/App/Help/Help.html.LyXconv/Help-Section-1.html#toc-Section-1

[joeqsmith]

There may already be some add-on software that would allow you to import a Touchstone file and run some of these simulations.   

[joeqsmith]

A sort of PAM4.   

[joeqsmith]

Short video showing how the eye diagrams would work.   

[joeqsmith]

I added support to synthesize both PAM-8 and 16 (shown with PAM-8 selected).  The time scale was corrected and the bit rate is now programed in Hz (shown with a 5Gb signal).   

The code was added to my PNA software.  Basically if you are running TDR, the eye is being updated live.  It would have been nice to have the newer 64-bit LabView for this but sadly, I can't do anything about it.   

While the Bonaguide and Jarvis book I referenced does explain the basic math in a paragraph, the Dunsmore book dedicates a few pages.  While he doesn't provide any of the basic details on how it works,  he does mention Keysight's Physical Layer Test Solution as being able to create eye diagrams from previously measured data.   It doesn't appear Keysight supports this software.  They offer a download but when you try and request a trial license, the website it broke.   

I have enough of the basics implemented and the next step is to sort out how to validate it.

[joeqsmith]

I thought I would search YT for any videos demonstrating the use of eye diagrams with a VNA.  Because the videos may cover a lot more than eye diagrams, I used the time link.   There doesn't appear to be a lot out there.  My short clip I made is coming up first in the search and that's bad.    If you are aware of others please provide the links.   

Now that I have the software finished up, my plan is to put some sort of demo together showing how it works and looking for ideas.   


Rohde Schwarz, Understanding Signal Integrity
https://youtu.be/anX8QZMhVjI?t=677

Anritsu, Signal Integrity testing with the ShockLine MS46524B VNA
https://youtu.be/tbyJdzYECv4?t=159

Keysight,  USB Type C Cable Compliance Test with Keysight VNA & Enhanced TDR Application
https://youtu.be/ejRdFSE7HR8?t=123

Keysight, Signal Integrity at 400G and Beyond
https://youtu.be/XwyTtCkUpwA?t=59

[joeqsmith]

Demonstration of the Solver32's eye diagram feature with the LiteVNA.   

[joeqsmith]

I decided to add the raw synthesized data to the display.   Because the math causes a phase shift, I have added a new button "PhaseTrim" that performs a cross correlation to correct for it.   You can also manually change the phase.  This has no effect on the measurement but rather is cosmetic allowing easier viewing of the data.   Attached showing before and after correcting the phase (cap6&7).

In addition to this I have made a few other changes before the release.   I removed the trim fringe feature as there was really was no value added.   The software now supports the Tab delimiter when importing Touchstone files.  Everything I have used was Space delimited.  Both are now supported.  It's automatic.   Keep in mind, my software is a poor excuse
for a viewer.  My only use for this feature has been debugging/validating my software.

I mentioned in the video how I limit the amount of data I process to ease the processing time.  I had someone write me once how they were trying to run some very low number of data points to increase their time resolution (ham) and how the software would hang.   As the software continues to evolve, I certainly give the users even more rope.  Still, I try and prevent some of the more basic conditions that can place a heavy burden on the CPU.    Currently I coerce the serial data's period / the step size between 1 and 2000.   I further limited the amount of data from 200k (demonstrated during the video) to 100k.   

Just an FYI about the 39pF // 10nH tank circuit I ran.  In case you were confused about why the software chopped off the settling.  I had said the rising edges, third dip was 11ns out and I setup to run it at 50MHz.   I set it to 40MHz to show the out of range.  This ranging error has nothing to do with why the software could not display it.  To measure this amount of time we would have needed to recalibrate the VNA using more data points.   This can be seen in Cap 8&9.

As I mentioned, the simulation doesn't consider any parasitics and we don't see the initial spike that we see with the LiteVNA.   While we did see this spike with the 30+ year old LeCroy DSO, it's amplitude was much lower.  Again, the DSO's pulser has a rise time of roughly 150ps.  The slower edge reduces the height of this leading spike.  When I synthesize the PRBS in software, it is perfect.  So after the convolution, we see a much higher spike.   

While I could have synthesized a waveform that was more representative of the DSO's pulser, or any source for that matter, I would rather see only the effects of the circuits I am looking at.   

***
Added Solver32 zoomed into initial peak, similar scale as LeCroy DSO (Cap10).

[joeqsmith]

YoutTube viewer Chris Scholz provided the following in regards to the eye diagram, signal integrity topic:

Hi Joe, I really enjoyed this video. A few years ago is was very involved in this industry.
May I recommend two more resources in addition to the commercial resources you mentioned in the first part of the video?

First, Packet Micro in San Jose has done quite a bit is interesting work on eye diagrams and associated topics in collaboration with EMStat.

Second AtaiTec, also in San Jose, has done pioneering work in the field of fixture de-embedding,
Keep up the great work, Joe!

https://www.packetmicro.com/
https://ataitec.com/products/adk/

[joeqsmith]

Anritsu paper with section on gating:
https://dl.cdn-anritsu.com/en-us/test-measurement/files/Application-Notes/Application-Note/11410-00722A.pdf

I added a simple gating feature to Solver.  Basically while time domain is selected, you can use the two cursors to define the window.  You can use the data within or outside of that window.   Attached showing my homemade 70mm air-line Beatty standard.  Red is the normal impedance and yellow after placing a window around the 70mm mismatch.   It supports both TDR and TDT modes.   

[joeqsmith]

I was testing using a modern PC and ran into a problem with the Intel Math Kernal Library (MKL) wrapper that is included with the version of LabView I am using.   Not a surprise as that version is now over 10 years old.   This has been an on going problem as Intel rolls out new hardware.   There  are a few posts about changing the MKS environment settings but it did not correct the problem.

One work around would be to go with a new version of LabView.  Even if National Instruments were to lower the cost (roughly $3000/yr rental fees) to $30/year, I wouldn't go that route.  The problem with LabView being and unique bastard child, if anything happens at NI, you are literally fucked.  With their new management, I have zero trust in the company and  without a perpetual license, I have no plans to consider this as an option.

The second option is not to be concerned.   Its only a problem as we start looking at modern processors with several cores.  Most commonly posted about is the AMD Ryzen™ Threadripper™ but I ran into it with an  i9-10980XE.   The software is only used by a small group and there are open sourced programs available.  This may be the best option.

The third option is to steal the 32-bit MKL wrappers from a newer revision of LabView.   I spent the day testing this and it seems to work fine.  This means that most likely I will create a new installer for the next release that has all the correct files.   The group who attempts to randomly install 63/32 bit versions of various releases of the runtime and VISA will now have an even more difficult time guessing at how to install it.   

[joeqsmith]

Gatesetup:  Showing poormans Beatty standard with bad connectors and bad layout.  We will measure S11 of the resistor attached at the far side.

Gate0: VNA was cale'ed at the cable connector and the Beatty standard inserted with DUT.   Yellow trace before adding port extenstion.   

Gate1:  Converting to time domain, we ca see the roughly 100 ohm followed by the 25 ohm sections and finally our 50 ohm test load.  Cursors were used to create a window around the two sections of mismatched line.

Gate2:  Setting the windowed area to a perfect line.  Red trace showing the raw data, Yellow is after windowing and converting back to frequency domain,  Violet is the load measured directly on the cable (without the Beatty standard).

Gate3:  Yellow trace is the effect of widening the window to include the hand carved 50 ohm sections of line and connectors. 

[joeqsmith]

Another example using a low cost 40dB attenuator and our  poor man's Beatty standard.  This time measuring S21.

gatesetup5_10:  Showing the setup with the LiteVNA, attenuator, Beatty standard and a section of semi rigid that is roughly the same length of the Beatty standard.   

gate5: LiteVNA was calibrated for 300k - 3GHz.  The attenuator was attached using an adapter directly to the test cables (violet).  The semi-rigid cable was then added (yellow).  Note there is a small difference but I am not taking care to torque anything and am just looking for a ballpark idea of how thing behave.   Next the semi-rigid is replaced with the Beatty standard (red). 

gate6:  With the Beatty standard attached, we change to the time domain mode and display the impulse waveform.  The cursors are placed around the reflections and the software then replaces this section with a perfect transmission line. 

gate7: We convert from time domain back to the frequency domain and display our corrected data (yellow).   

Of course, that Beatty standard would represent a VERY poor test fixture but it should provide some insight how the time gating could be used to correct for these kinds of errors. 

[joeqsmith]

This example shows using the inverted window where everything outside of it is replaced with a perfect transmission line.

gatesetup10_14:  This is our really bad setup showing two Beatty standards on each port with our DUT stuck in the middle.  The DUT is one of those really low cost 3dB attenuators. 

gate10:  LiteVNA was caled and the attenuator was placed between the two ports using an adapter (violet).   The two Beatty standards were then added along with a few sections of coax (red). 

gate11:  Changing to time domain and looking at the reflected step response of the whole mess, we can see the we start out at 50ohms, then step to 100 ohms, then down to 25.  This is the first standard off of port 1.  We then work our way through the coax to our attenuator and then to the second 25 ohm Beatty standard. 

gate12:  Changing to the transmission impulse mode, we set the cursors to the area between the two standards where our attenuator is located. 

gate13:  Converting back to frequency domain, we now see our windowed area (yellow).   

[joeqsmith]

Calibrating the Lite, and then swapping out the thru standard (violet) for the FR4 standard (red).   Attemping to correct it (yellow) we seem to be at the limit.   May need to characterize the standards and ditch the ideal model.

[joeqsmith]

Checking Dislord's Github account, seems they may have stopped all of their firmware. 

Testing this bug, it is easy to reproduce and has been included in the LiteVNA for as early as I have firmware for it.   You can produce it with the LiteVNA running stand alone.  No PC.   It will also replicate on the second unit and I suspect a firmware bug. 

To produce it, leave both ports on the Lite open.   No need to calibrate it.  Display S21 logmag.  Sweep from say 1G to 5G by setting the start and stop.  You should see some low values.  Now set it to CW at say 5G.   You should get some same low value.  Now set it to CW at 5GHz again.  The signal should jump about 6-10dB.    You can set the start and stop again to reset it. 

It appears that the first time CW is entered, the data is correct.  Selecting it again, it's off.   It looks like it may have something to do with the IFBW and maybe something to do with if it is sweeping prior to selecting CW.   I've just been working around it just by being aware of the problem.   If you use my software, you can just select CW twice to see the change. 

Attached picture YELLOW showing S21 after selecting CW the first time, and RED after selecting it again.   Again, you do NOT need my software or a PC to replicate the problem. 

***
Also, I should mention that it doesn't appear to have anything to do with the number of data points selected or the frequency range.   It does however appear to shift more the higher in frequency.  I have been attempting to use the Lite above 7GHz.    At 3GHz, I see maybe 0.4dB shift.  At 9GHz, roughly a 10dB shift. 

[Kean]

Checking Dislord's Github account, seems they may have stopped all of their firmware. 

Dmitry* (DiSlord) is from Russia.  He seems to have not posted anything here or checked in code to Github for some months.  Hoping he is OK.

* his full name and email can be found in the copyright/left messages of his code

[joeqsmith]

I sent him a note.  Hopefully his absence is temporary.  Considering the state of the original NanoVNA's firmware compared with the LiteVNA, I don't see anyone else stepping in and providing that level of stability any time soon. 

[DiSlord]

On my device i see small jump near 2dB

In CW mode device work as generator and not switch output for measure (it measure reference one time at set freq and after measure reflect and thru, but not disable output for measure reference).
Look like on second set CW mode on equal frequency in not reset state, and reference data not correct

I try research this problem

[DiSlord]

I hope fix this problem. Now i reset state and remeasure reference on CW mode if set equal frequency again

[joeqsmith]

Glad to see you are still with us and doing ok. 

I am testing the new firmware now and it does correct the problem I mentioned.   As much as I have been using the LiteVNA I would expect to stumble onto a few problems but this is the only one I noticed.   I'm very impress with how good both the hardware and firmware has been.   

Thank you for your your help and try not to be a stranger.