Storing Data Fast

[jpanhalt]

I have decided to try using a 3 MSPS ADC (16-bit, e.g., a ADS7885 or similar ADC) to allow digital filtering of a relatively low frequency (center at 500 kHz, bandwidth < 1 MHz) signal.   Ideally, I would like to record for 1 second, but recording for 300 millisecond would be OK.  Presumably, some sort of DMA controller and memory (FRAM?) is needed, but the number of offerings are staggering.

How does one get from the raw ADC output to a memory that can be accessed at relative leisure?  Any specific suggestions?

Regards, John


 

 

[w2aew]

While I don't have any specific recommendations (I'm really more of an analog guy), the common way to do this as ADC speeds ramp up is to immediately DMUX the data samples into several parallel paths that are written to memory at a more leisurely writing rate.

[David Hess]

3 MS/sec with 16-bit words is pretty slow on the scale of things.  Ancient digitizers handled faster data rates with just TTL logic.

A 333 nanosecond cycle time is so slow that it could be divided into 2 phases leaving 150 nanoseconds to update the address counter and 150 nanoseconds to write the data to RAM.  A discrete logic DMA controller for this is trivial but most designers would use a small CPLD or FPGA.  The logic only has to deal with the address and control lines and not the 16 data lines.

1 second at 3 MS/sec is 3 million words.  3 million 16 bit words is 48 Mbits.  That is larger than available SRAM parts but two 2Mx8 SRAMs (16Mbit and about $10 each) would be good for 2/3rds of a second.

A design using a single 8 bit wide DRAM and more complex logic would be less expensive and have a much longer recording time.