Half-decent diy RF generator utilizing AD9951 - an idea

[phenol]

It is going to be sensitive to power supply noise if the internal PLL is enabled. I guess it would be fine with a generic 1117 and an external reference clock, but you still have to exercise great care with the external PLL source as it WILL be sensitive to any sort of noise that can modulate the VCO. You could use capacitive multipliers to filter the power for the sensitive parts of the reference source.
I went medieval on it and made an analog-only 10x multiplier that multiplies an external 100MHz OCXO signal in 5x and 2x stages to clock AD9910. 3 different versions of it. No PLLs, no VCOs.
One important feature of AD9951 that is missing in AD9910 is the DACBP pin. The external capacitor connected to that pin filters the bandgap DAC reference. The unfiltered bandgap noise manifests itself as somewhat elevated AM noise in AD9910...

[Yansi]

Looking through the datasheets, even the AD9957 does not have the DACBP pin. Doh! Hopefully it ain't not that bad.

Currently designing the oscillator section on the AD9951/4 module, I have stumbled across this in the documentation. It seems they (Analog Devices) know well the internal PLL is junk. The datasheets tells you exactly to use external REFCLK when higher performance is required.

For best phase noise performance, a clean, stable clock with a high slew rate should be used to drive the REFCLK pin and bypass the multiplier.

[Yansi]

Finally, the AD9951/9954 module is done.  I have put in a lot more time than originally intended, but whatever... Not the best of layouts, but maybe better than the Chinese ones. I think it is good enough for a 2-layer jobbie.

Have managed to squeeze almost all functionality on that little 50x50mm board, except the COMParator in the 9954 that I don't care of and the XTAL_OUT pin that likely won]t ever be needed, as it will likely be supplied using the REF input with external CLK source.

If you see any major fail in there, please scream. I will have it sent to be manufactured on Tuesday otherwise.

//EDIT: Corrected schematic file.

[ogden]

You shall read AN-837 regarding filter layout. Also line between filter and socket does lot look like 50 Ohm conductor-backed coplanar waveguide  (CBCPW), but luckily it's short.

http://www.analog.com/media/en/technical-documentation/application-notes/351016224AN_837.pdf?doc=cn0304.pdf

http://wcalc.sourceforge.net/cgi-bin/coplanar.cgi

[Yansi]

Why doesn't it look like a 50ohm CBCPW? 

Putting the dimensions I used into your calculator yields 50.8 ohm characteristic impedance, so what? I think you can't make that much better, considering manufacturing tolerances.   I don't get it where you see the problem. (H=1.5, W=1.26, S=0.25, T=0.035, eps_r=4.7)
 
But thanks for mentioning, you have forced me to to look up what material exactly will the manufacturer use. The eps_r is slightly lower than I have expected (4.4 actually), so I will correct my design for that. It would be 52ohms otherwise, which I don't think would be a major problem of any sort.

I have seen that exact filter app note somewhere.  It is nice, but I have followed the evaluation board for that AD9951. I guess making the shunt caps symmetrical would help, however it would mess the filter a bit up, as I could not combine the specified values using two caps  in parallel.  Currently I am not willing to spend time fiddling and redesigning the filter.

Regarding the last paragraphs of AN-837 linked above, I have done this way:
 - I have solid uninterrupted ground plane below all RF circuitry. I have also top layer ground plane near the filter, as they are suggesting.
 - Capacitors unfortunately not split, due to reasons stated above. (not willing to spend time redesigning the filter to account for slightly changed capacitance not being able to combine the required ones from two caps). Multiple vias used on the ground lead of the shunt capacitors.
- Regarding placement of filter components - didn't exactly try to make it crowded, but I don't think that having the components far apart will help with anything. In fact I think it get worse.
 - Components ... well. I will use whatever will I be able to find. At least for the prototype.
 - Traces external to the filter when possible are 50ohm (at least on the output side)

Do you have any specific ideas how to make the filter layout better?

//EDIT: Fixed a lot of typos. Added dimensions of the CBCPW.

[ogden]

Why doesn't it look like a 50ohm CBCPW? 

Putting the dimensions I used into your calculator yields 50.8 ohm characteristic impedance, so what?

It just seemed to me that S is too small compared to trace width. If you verified and it's 50 +/- few ohms then it's completely fine, end of the story. - Especially for length of the track which is close to nothing.

not willing to spend time redesigning the filter

Sure it is not that important, especially for first prototype. Just wanted to let you know such article exist. After all frequencies they fight in the article are above 400MHz.

Do you have any specific ideas how to make the filter layout better?

It's good already. You can possibly flip it vertically so power trace is not so close to filter components.

[Yansi]

Ok then, I will get it manufactured. We'll see how good or bad it will be.

Now a rather lengthy post, sorry for that. But many thanks for reading throuh!

Meanwhile, I started prototyping the ALC module. I am not sure what the best topology should be and I'd like to discuss that a bit.

First we need to solve for the DDS output signal level: The DDS dac is set at it's nominal current of 10mA. As the loading impedance is 50ohm (differentially, using a proper balun trnasformer), I will get a 500mV peak-peak signal into the 50ohm load. (Each leg of the DAC drives a 25ohm load, meaning a maximum 250mV per leg.)  That means I will get about 1.25mW (+1dBm) of power out of the DDS.

Now considering the insertion loss both of the balun (which can be up to 3dB at the edge of the band) and considering insertion loss of the filter which is currently unknown (guessing few dB will be lost in there to), I will likely end up with something in the range of -1dBm downto -5dBm. But we'll measure that later exactly.

To ease the ALC design, currently I will be fine with getting only +13dBm out maximum, as I can use general purpose MMIC ICs for that sort of range. In fact, I need a +19dBm or more of output from the MMIC. Why?  The output has got a 50ohm series resistor. That means the MMIC will need to deliver 40mW (+16dBm) into 100ohm load.  Now the MMIC is loaded only with a 100ohm load, I will add a second load of 100ohm, which will be the input of the log. detector. Now the MMIC is loaded properly with 50ohm, but needs to deliver 4 times the output power of the generator, i.e. +19dBm (80mW).

So I need to be able to amplify those -1 downto -5dBm  to +19dBm.   So I need at least 24dB of gain. Supposed the output MMIC (likely SGA6389Z) will have a 15dB of gain, I will need a second amplifier delivering the missing 9dB (will likely use a MMIC with a higher gain than that and add a fixed attenuator). So far so good.

The question is: Should I put the variable attenuator in front of the two amplifier stages, or should I put it in between?
I see both advantages and disadvantages for that. Let my try formulate those I came up with:

MMIC in front of the amps:
 - both amps working full gain even with the smallest amplitude. As the overall gain of the MMICs combined will be from 30 to 35dB, I guess this will give a worse noise figure. Question is, does it matter so much here? We are working with mV signal levels, not uV.
 + the first amplifier will work with the least amount of signal level possible, giving least amount of distortion.

MMIC in between the AMPS
 - first stage amplifier working with high signal level, as it both must feed the second stage and also cover the insertion loss of the variable attenuator -> higher distortion. (it seems the first amp will need to give up to +8dBm continually in this case)
 + probably better noise figure, as the signal levels will be higher.

I do not have enough experience to judge here, but guessing noise figure is not much in play here, as we are working with quite large signals anyways. So maybe the the first option (variable attenuator in front of both amps) is the right to choose here. Signal purity (low distortion) should be preferred, rather than a few dB of added noise. What do you think about that?

I can now clearly see, why the Marconi generator has the variable attenuators distributed in between all amplifier stages. It combines the advantages of both solutions.  But I think it will be enough in here to use a single variable attenuator in front of both amplifier stages.

Here's the schematic I am working on. The first stage is MAR-3SM - chosen based on the P1dB requirement - it's the only one I have here that will be sufficient, apart from an overkill like ERA-5 (I have those too). The PA will be SGA6389Z (now obsolete, but who cares for one off projects), I can get those, or the Onsemi MMG3H21NT1 (in that case I'd probably choose an amp with less gain for the first stage)

(Note the slight hack of the MACOM variable FET attenuator. I don't want to bother with negative voltage rails)
(Note2 the input pad will also make the input match better as a load for the DDS filter, too which it will be connected)

BTW: Does anybody know if the FET attenuator should have a DC return to ground from the RF ports? The datasheet doesn't say shit about that or about how much current the control pin needs.



//EDIT: Added Note 2, fixed typos

[xaxaxa]

Are the sma connectors going to be mounted on the top or bottom side of the pcb? on the top side the body of the connector will "pinch" against the rf trace and mess up the impedance near it; with this layout be sure to put the sma connectors on the bottoms side.

[Yansi]

That is a correct note (I usually do not press them directly against the board), however what will mess up worse: Connector fitted from top or a nasty layer switching hack using a VIA to the bottom side? You tell me...
 I think the RF via is much nastier thing on a 2-L board then a trace being in close proximity of the SMA jack body for a half a milimeter or so.

Unfortunately, I do not have those pcb side SMA, only these right angle ones or straight ones.

[Yansi]

Should this really be better, than a trace sneaking under the connector?

[xaxaxa]

At <100MHz it probably doesn't matter, but higher than that i'd go with an edge connector or just solder it on the back side; is there a reason the connector can't be on the back side?

btw straight sma connectors can be edge mounted too

[Yansi]

Here we are talking about up to 160MHz and 400MHz.

Why not soldered bottom?   ... cannot find the puking smiley ...   THT components have only one place: On the top of the board.

Yes, they can be edge mounted. But it is also a nasty hack. Why not doing it properly?

That would be like this... having THT stuff sticking from it in every possible direction. Yuck!




//EDIT: Maybe I could cobble up a board just to test the behavior of the vias/connectors and measure it using a proper VNA. That might be an interesting idea to do. Like Analog did the research with the filters.

[TheUnnamedNewbie]

Ok then, I will get it manufactured. We'll see how good or bad it will be.

Now a rather lengthy post, sorry for that. But many thanks for reading throuh!

Meanwhile, I started prototyping the ALC module. I am not sure what the best topology should be and I'd like to discuss that a bit.

First we need to solve for the DDS output signal level: The DDS dac is set at it's nominal current of 10mA. As the loading impedance is 50ohm (differentially, using a proper balun trnasformer), I will get a 500mV peak-peak signal into the 50ohm load. (Each leg of the DAC drives a 25ohm load, meaning a maximum 250mV per leg.)  That means I will get about 1.25mW (+1dBm) of power out of the DDS.

Now considering the insertion loss both of the balun (which can be up to 3dB at the edge of the band) and considering insertion loss of the filter which is currently unknown (guessing few dB will be lost in there to), I will likely end up with something in the range of -1dBm downto -5dBm. But we'll measure that later exactly.

To ease the ALC design, currently I will be fine with getting only +13dBm out maximum, as I can use general purpose MMIC ICs for that sort of range. In fact, I need a +19dBm or more of output from the MMIC. Why?  The output has got a 50ohm series resistor. That means the MMIC will need to deliver 40mW (+16dBm) into 100ohm load.  Now the MMIC is loaded only with a 100ohm load, I will add a second load of 100ohm, which will be the input of the log. detector. Now the MMIC is loaded properly with 50ohm, but needs to deliver 4 times the output power of the generator, i.e. +19dBm (80mW).

So I need to be able to amplify those -1 downto -5dBm  to +19dBm.   So I need at least 24dB of gain. Supposed the output MMIC (likely SGA6389Z) will have a 15dB of gain, I will need a second amplifier delivering the missing 9dB (will likely use a MMIC with a higher gain than that and add a fixed attenuator). So far so good.

The question is: Should I put the variable attenuator in front of the two amplifier stages, or should I put it in between?
I see both advantages and disadvantages for that. Let my try formulate those I came up with:

MMIC in front of the amps:
 - both amps working full gain even with the smallest amplitude. As the overall gain of the MMICs combined will be from 30 to 35dB, I guess this will give a worse noise figure. Question is, does it matter so much here? We are working with mV signal levels, not uV.
 + the first amplifier will work with the least amount of signal level possible, giving least amount of distortion.

MMIC in between the AMPS
 - first stage amplifier working with high signal level, as it both must feed the second stage and also cover the insertion loss of the variable attenuator -> higher distortion. (it seems the first amp will need to give up to +8dBm continually in this case)
 + probably better noise figure, as the signal levels will be higher.

 
//EDIT: Added Note 2, fixed typos

There are two things that drive this design: The small signal performance of the amplifier (=noise) and the large signal performance of the amplifier (=linearity).

For obvious reasons, you have to keep your signal above the thermal noise floor at all times. If you want a SNR of 70 dB at your output without any fancy filters or whatever, you need to have that SNR be above 70 dB at all times (I just chose a random number, plug in your SNR). I don't know what your target output power range is, but if you want to get a high SNR at the output, it means that at no point in the signal path, with maximum attenuation, are you allowed to have less SNR. Sounds obvious, but I am just making sure that we keep that in mind!

At the same time, you want to signal at your amplifiers to be as small as possible, such that they are as linear as possible.

This is why you might find alternating variable attenuators and amplifiers - keep riding the sweet-spot between noise and linearity as long as possible (in addition, it can mean less variation in the signal levels of the amplifiers with respect to operating settings, which means less thermal drift issues to deal with).

In addition, if you have some padding between amplifiers it can result in higher stability. The same goes for power rails - you might have to best S11 and S22 of your amplifiers, and the simulations all say it should be stable, but then suddenly you have oscillation because your power rail acts as a feedback path. Make sure you have a lot of filtering on there.

Don't underestimate noise though. You have wide-band circuits, which means the thermal noise might be higher than you expect...

[Yansi]

re are two things that drive this design: The small signal performance of the amplifier (=noise) and the large signal performance of the amplifier (=linearity).

I have already figured that out, as seen above.  However the "dB noise figures" of the RF amps are still a mystery for me. I am familiar with noise calculations regarding standard AF amplifiers and stuff, but the approach used there seems to be very different.

How can one calculate the noise floor of a RF amplifier? For example, suppose we have the two cascaded stages consisting of MAR-3 (12.5dB gain, 3.7dB NF) and second stage of SGA6389Z (16dB gain, 4.2dB NF). How can I calculate using just that, what is the smallest signal possible, to achieve a 70dB SNR at the output? Or do I likely need more information than this to estimate the output SNR?

The signal levels were already stated in the thread: Originally I wanted a +20dBm out. As that requires  a discrete output stage, I have temporarily backed off with just a MMIC amp, as that way I could produce up to those +13dBm, which is enough for most applications.

[Yansi]

Well, after spending a bit on google, it seems the calculation concepts may not be that different.

Based on this PDF I have found: http://www.imst.de/itg9_1/vortraege/oktober2001/koenigsmann_folien.pdf

The noise floor (noise power) at normal temperature is -174dBm/Hz.  Fine, I get. But how do I calculate the noise floor?  I need a say 160MHz of bandwidth, that would mean I need to add 10log(160E6) = 82dB to that -174dBm figure. But wait - the amplifiers bandwidth is not limited - at least the schematic I came up with does not limit the bandwidth intentionally. Is that a problem? As in this case, the amplifier would work well above 2 GHz. That would result in a figure of like 97dB (considering like 5GHz BW), instead of 82.   What to do with this?

Then there is the noise figure of the amps. The combined figure of the two is NF = F1 + (F2-1)/G1 = 2.34 + (2.63-1)/17.8 = 3.86dB noise figure. (Look at the slide 14 of the PDF above, I am not sure if they calculate the gain factor correctly - as 20dB amplifier neither does have a 100 times voltage gain, neither a 100 times power gain. A mistake?*)

So now we have -174dBm + 97dB + 3.86dB = -73dBm noise floor. Doesn't sound the greatest result of all times, but well.. the cascade has 28.5dB of gain on a bandwidth in GHz digits. And also the output signal I want to be on the scale of +20 downto 0dBm or so, meaning resulting SNR from 93dB to 73dB.

Those 90+dB SNR looks good, but those 73 not so much, but it may be sufficient for an application where the expected SFDR is like 65-70dBc.

Or have screwed somewhere? What about the bandwidth? How should I calculate that?

//EDIT: *Have verified from multiple sources, the cascaded NF calculation in that presentation seems correct. Verified the calculation on this website, guesssing Pasternack should be very reasonable to be trusted: https://www.pasternack.com/t-calculator-noise-figure.aspx It came up with the same value of 3.86dB.

[RadioNerd]

You are mixing up power spectral density (in dBm/Hz) and absolute noise power (dBm or Vpk-pk)
PSD is only affected by the noise figure bit is independent from the bandwidth of your system (ie noise floor of a spectrum analyzer).
Absolute noise powe however is, and thats for example the reason why high-speed scopes look noisier than band limited ones

[Yansi]

If one needs the noise power, one takes the spectral density and multiplies by the bandwidth. In decibels, it is the same as adding those together. I do not see what I have done wrong. Please explain.

Noise power  Pn = k T B = -174 + 10log(B)  [dBm]

[RadioNerd]

Yes, that's right. I was mainly confused about how you use the term noise floor... For me, noise floor implicitly means a spectral density (i.e. as you see it on a spectrum analyzer). In that case, the noise floor after all stages (again in dBm/Hz) is simply -174 dBm/Hz + total amplifier gain + cascaded noise figure...

In my opinion, calculating the absolute nose power is only of interest if you are going to use or look at the signal in the time domain, i.e. using an oscilloscope or a very fast ADC. In this case absolute SNR (within the BW of your receiver/measurement equipment) is much more of concern.
If you don't have a 5 GHz scope or similar you will never see the full noise power as all systems are inherently bandwidth limited.

The main problem I see is that too much noise power can limit the dynamic range of the ALC loop as you are planning to use a wideband detector. But you probably still have quite some headroom there...

[Yansi]

If I need to calculate the output SNR then after the amplifier cascade: It is a ratio of the signal vs. the noise floor, as I understand it. (My terminology may be a little off, having hard time with the translation)

You stated that the noise floor, as seen on the SA, is without multiplying by B, i.e. one gets the spectral density instead. Okay than, but then there's a problem I think:

SNR is by definition the ration of signal and noise power. How am I supposed to calculate the SNR at the amplifier output, if I can not use the whole Pnoise formula, as it would account for all he noise in the specified bandwidth?

It seems that SNR needs always to be specified  for an amount of bandwidth, as the SNR is directly proportional to the bandwidth itself.

But I understand your point the the wide band log detector. The AD8307 can detect pretty much above those 500MHz. It therefore seems right to have a band limiting filter (low pass) in front of the wide band log detector, to not detect the power of out of band noise. Which makes sense. 

In this case I need only a 20dB range at the the output so I think the full bandwidth output noise power may not be an issue (yet). But as I will need higher output power range, it may become an issue. Is that correct?

[Yansi]

So a set of a new question, as those above does not seem attractive 

Currently am solving an issue with the wide band MMIC amplifiers.  Specifically:

1) The DC blocking capacitors.  As I need a very wide band operation (100kHz up to hundreds MHz), I don't think that a single capacitor will work. I need it to have a very low impedance at the band of operation, ie. both at 100kHz (which seems like I need like 1uF cap there) and even at the high end (hundreds MHz).  So it seems likely I need to use at least two caps in parallel, expecting the 1uF not to work well at the mid- and high- band frequencies.

What combinations should I use there? Currently I have put there 1uF + 1nF, but am not sure I should use a larger value second cap, otherwise the impedance spike from the larger cap will happen early before the other one has low enough impedance.

Looking in the Marconi schematic (again!) they use "just 220nF" output capacitor for the whooooole range of 80kHz up to 1040MHz and a set of small (even series connected) 39nF caps in the small signal section. Thats interesting. I don't quite get how that works at the low end.  Single 39nF cap has impedance of 51 ohm at 80kHz. If there are even three in series, that is quite some amount of attenuation due to weak coupling.

2) The broadband RF chokes for the bias. The same applies here. I need a broad band choke to operate within like 100kHz up to 500MHz. What I have done already, I have split the choke into two series ones. But I think here applies the same as for the capacitors, regarding the impedance. I need the SRF of the smaller one to be above the maximum operating frequency, but the SRF of the larger one to be high enough as when the smaller one stops operating (is low impeadnce to the operating frequency), the larger one takes all the work. What values should I use? (In the marconi there is a 2.4uH + 1000uH combination at the output stage).

[xaxaxa]

So a set of a new question, as those above does not seem attractive 

Currently am solving an issue with the wide band MMIC amplifiers.  Specifically:

1) The DC blocking capacitors.

In some cases a single large cap will work; as long as the cap has very low ESR at the higher frequencies, it doesn't matter that the resonance peak is at a lower frequency, because at worst the impedance of the cap is no worse than a equivalently dimensioned metal link.

2) The broadband RF chokes for the bias.

Above the SRF of the lower frequency choke it looks capacitive, so you need to make sure that that capacitance does not resonate with the high frequency choke to form a low impedance. For the higher frequencies you might want to look into smt ferrite beads as well, as ferrite beads can have a high impedance over a wider frequency range than inductors, as well as offer some resistive impedance so helps with the resonance problem. FBMH1608HM601 has high impedance from 20MHz to >3GHz. Combine this with some (through hole?) larger ferrite bead and you could potentially get a nice ultra wideband choke. Check with spice/rfsim99 to make sure there are no resonances.

[Yansi]

So you think that probably using a single 1uF capacitor may be just enough?   Or could there be some unforeseen problem combining a larger coupling cap with a smaller one, to improve at the high band end? Like 1uF + 10nF, or there is no point in doing that?


Nice find with the ferrite bead. I did not think these could be used too.  The impedance curve looks good enough for sure, in between the 20MHz to GHz range. Price is good to.  But still need to find the other choke to complement this one, as for the low band region from 0.1 up to some tens of MHz.

Btw, just thinking about it... if the bead is supposed to have Z = 200ohm at 20MHz (according to the FBMH1608HM601  datasheet and the DCR is just below 0.2 ohm, it means it looks like a 1.6mH inductor at 20MHz. How do they do that?

[xaxaxa]

So you think that probably using a single 1uF capacitor may be just enough?   Or could there be some unforeseen problem combining a larger coupling cap with a smaller one, to improve at the high band end? Like 1uF + 10nF, or there is no point in doing that?

I just did a search and it seems very few manufacturers quote ESR or impedance values for chip capacitors in the nF - uF range; personally i'd measure a few caps and see whether their impedance at high frequency is low enough; if not, you can parallel several caps of different values and check with simulations to make sure there are no resonances.

Btw, just thinking about it... if the bead is supposed to have Z = 200ohm at 20MHz (according to the FBMH1608HM601  datasheet and the DCR is just below 0.2 ohm, it means it looks like a 1.6mH inductor at 20MHz. How do they do that?

My calculations say 1.6uH at 20MHz, which is easily achievable btw also found the FBMH1608HM102 which extends the frequency down to about 10MHz.

A quick search on mouser didn't turn up any suitable low frequency beads, so you may try an inductor or wind your own; then simulate the combination in spice or rfsim99 (googling "FBMH1608HM102 spice" turns up the models).

[Yansi]

Yeh, I have found later I have pressed the wrong button on my calculator. Of course it is 1.6uH.

Still have not found a suitable inductor to complement the ferrite bead at the low band end though. 

[Yansi]

While not being able to find a suitable inductors, some progress is being made with the ALC PCB module.

Well it might look a bit over engineered looking on those six SO-8 packages, but indeed it is and for a purpose. I'd like to have that ALC block available as a more permanent one, so I have added some more support circuitry in there like a calibration E2PROM and a output unleveled comparator. Also the module is designed to fit inside an off the shelf tin shield box, sticking all connectors outside, including two status LEDs.

On the other hand it is quite under engineered on the RF side of the thing. Hopefully, it will work. At least a bit, so I won't get too much disappointed.