I had thickened the Cu layers as well, no difference. I removed the vias to speed the tests but saw no major change. I noticed you are using 4. I could add them back in if you want to provide details about them.
The width of each top side plane is 351mils or a total width of 981mils
Cu conductivity is set to 5.8e7 S/m
FR-4, 62 mils thick, Er 4.6, Loss Tan 0.02, Conductivity 0.0 S/m, Mrel 1.0, Mag Loss Tan 0.0
Ports resistance is set to 50 ohms (license prevents any changes)
I'm using an inch from the top of the CPW to the box, air dielectric
I'm not using the de-embed feature, symmetry
The attached Touchstone is with the above setting and matching the AppCAD drawing. I doubt any of this will matter and suspect there is some difference in the simulators that causes this error.
If you want to see if the two simulators will show somewhat of a trend, I reduced the width of of the signal trace from 113 mils to 16 mils. No other changes were made.
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Using the baseline from AppCAD, I then changed the dielectrics thickness to 10mils.