Testing the effects of releaving ground plane beneth a component

[joeqsmith]

Question is still if cutting the board will cause a large enough change to be able to detect it.   I think we already have that answer.   Looking at that data, it does seem very bad.    I suspect a crack and reflowed the joints.  Connectors were clean.  Terminator appears fine.  May have cracked it at some point or it was never soldered in the first place.  It's been badly abused. 


originaltest1_new: Showing all the data from test1 prior to the cut compared with the data I collected tonight. 

originaltest1: Showing all the data from test1 (prior to the cut) normalized to trace1.   Looks bad.

HAND: data from tonight showing hand tightening, normalized to trace1.

TORQUE: data from tonight showing torqued, normalized to trace1.

combine:  All the data from tonight, normalized to the mean. 

Guessing a bad joint.

[MartinL]

Just want to echo the point about cracking. The ceramics used in SMT MLCCs are very brittle and can easily be cracked by flexing of the PCB, particularly if the board is thin and the capacitor is tall.

A while ago I had to diagnose a small collection of failed 60GHz radar boards. After a lot of head scratching, the thermal camera revealed that some of the decoupling MLCCs in the power supply section were getting hot. Removal and measurement showed them to be shorted; replacements worked fine. All were top-spec AEC-Q200 genuine Murata parts.

The cause was cracking from mechanical stress on the board, but the damage was almost invisible. See attached photo.

The only mechanical stress these boards had been exposed to was being pushed onto stacking connectors of a mating board by hand.

[joeqsmith]

I looked at the free version of Sonnet.  It was too limited to get anything working.  So I tried an old version of Ansoft.  I was able to get a simple EM simulation to run and even tried creating a model based on the Touchstone file.   Both ran fine however, once again it appears too limited to allow simulating what the OP had asked about.  I am not aware of any other free tools.     

http://www.gunthard-kraus.de/Ansoft%20Designer%20SV/English%20Tutorial%20Version/index_english.html

[G0HZU]

I looked at the free version of Sonnet.  It was too limited to get anything working. 

If you register the Sonnet Lite version you get a free increase from 1Mb to 32Mb memory. I assume Sonnet will send you a free flexlm licence locked to your PC to allow the 32Mb memory upgrade.

32Mb is quite generous and should be more than adequate for the stuff you are looking at.

[joeqsmith]

I am not familiar with any of these tools but with your experience, are you sure it would even be able to run this little demo?   It looked like there was no way to split the ground plane.  I was going to attempt to remove it and add another signal layer.   I also wasn't sure if I could import the Touchstone file into the EM model. 

With you having the full blown tools and the experience with them, how difficult would it be to set up the simulation and run it?

[G0HZU]

I think the Lite version will be able to do the ground plane split and model an air layer above and below the PCB.

One limitation will be that the cap model is for a perfect capacitor so there will be no package inductance or loss in the cap model. Also, the EM simulator can't model the interaction between the PCB and the body of the cap unless the cap is crudely modelled as a brick of dielectric. I think this is only supported in the full version. Even then I'm not sure how realistic this will be because the real cap body will also contain multiple inner plates of metal.
The s2p models from ATC will be taken over a PCB with a regular ground plane so this won't be quite right either if you then cut away the groundplane in Sonnet.

Try registering it to get 32Mb and then set up the box, the layers and then add the metal for the top microstrip and add the ideal cap. You can then edit the groundplane by adding an air layer below the main PCB. This creates a lower layer for your PCB that you can edit. When you do this you have to draw the PCB ground plane details yourself as it will start with no metal on this lower PCB layer.

[joeqsmith]

Can you split the ground plane with the full blown version?

I see no reason why a capacitor would be required other than this is what the OP had asked about.   They haven't chimed in, so I doubt have any interest in it.   Still, I'm curious how close any of these simulators would predict the effects.   Do you have any better ideas how to proceed?   

Based on the little I have no played with these different simulators, I am thinking just go with their first test:

1. A 50-ohm microstrip with two SMA connectors, far-end terminated by 50-ohm coax load. One board has solid ground plane and another has cut out under the center conductor for impedance compensation.

The problem with Sonnet would be splitting the plane.  I suspect the same is true for Ansoft.   

[G0HZU]

You can split the ground plane with both the Lite and full versions of Sonnet. Even if you don't register it and use 1Mb memory you can do these things in Sonnet Lite although you would be limited in PCB size and by how much metal you can put on the board before it goes over 1Mb. I think the Lite version also only allows a few layers before it hits a limit but this won't apply in your case as you don't need many layers.

[coppercone2]

solder very thin long dummy resistors in random places of the PCB to see deflection, if there is stress on the board you should see bowing under a microscope.

[joeqsmith]

As I said, there appeared to be no way to change the ground plane.   The only work around I could come up with was to create a separate signal layer and use that as the ground but the simulator complains about the number of layers for the free license.   But again, you use it on a professional level and I expect you could knock it out in a half hour or less.  Or, is the tool far more complex to use? 

[joeqsmith]

From the manual:

GND Level: You can place polygons on the GND level, but they have no effect
because this level is already completely metalized. However, cases do exist in
which you may want to place a polygon on the GND level in order to place a via
or a dielectric brick there.

Obviously, this is not true as you use the tool.  I suspect I am just not understanding what this statement is suggesting.

[G0HZU]

What they are referring to there is the 'box' GND. You can't edit this because it is meant to be a perfect ground at all times. You can think of the EM simulation happening inside a perfect metal box that is a perfect ground everywhere on the walls and the bottom face. However, just like you can put a 2 layer PCB inside a box you can put a two layer PCB inside the perfect Sonnet box.

[G0HZU]

In other words, the simplest PCB simulations let you use the box ground as the bottom layer of your PCB. I think this means the simulation will use less resources and will run faster. You can connect vias to the box GND but you can't edit the box GND layer 'artwork' because it has to remain perfect. If you want a 2 layer PCB where you can edit the lower layer to make it less of a perfect ground plane then you have to float it above the box ground just like you would in a real box.

[joeqsmith]

If you want a 2 layer PCB where you can edit the lower layer to make it less of a perfect ground plane then you have to float it above the box ground just like you would in a real box.

Which is what I was suggesting when I wrote:

The only work around I could come up with was to create a separate signal layer and use that as the ground but the simulator complains about the number of layers for the free license.

  It seems that the free license will not allow for that added layer.   This new floating ground could be attached to the boxes ground with vias as well.  Otherwise, I suspect there would be a limitation on the number of ports.  It's such a simple project but seems to require a license.   

I added a second signal plane with the free version of Ansoft and I don't think the license was a problem.  I ran into problems when trying to simulate the capacitor rather than using a lumped model.  If I remove that constraint, it may be possible to use that tool. 

[joeqsmith]

Do you actually have the full license for Sonnet, or are you using one of the limited licenses?   I should have asked but assumed with it being for work you had the full blown license. 

[G0HZU]

The works licence has full memory and a few basic options including the Genesys co-simulation option. This was purchased back in 2004 and I use the Sonnet engine via Genesys. In other words I do all the PCB design and circuit design in Genesys and then Genesys asks Sonnet to simulate the PCB layout. The results get automatically sent back to Genesys and Genesys graphs the results.

Have you checked what metal layers you can see? You should have 0, 1 and GND where GND is the box GND and layer 1 is your editable ground. Layer 0 is the top microstrip layer.

[joeqsmith]

Makes sense.  I saw they had support for other layout tools as well as DXF.  The DXF requires the LitePlus license.  It gets you 6 ports and a few other features.     

They claim 2 metal layers with the Lite, which I would have assumed did not include the box.  They also allow 4 ports so you would think the design could just float in the box.  Guessing I am missing something.

[joeqsmith]

Even two more vias will throw it over the 32M.   The $500 license wouldn't seem to add enough to make it worth while. 

[joeqsmith]

Showing estimation with 8 vias and also attempting to run it. 

32Mb is quite generous and should be more than adequate for the stuff you are looking at.

While its the basic coplanar with a slit in the ground plane, there's no point in spending the time to make everything correct.   I just wanted to get some idea how much memory it will require.   From your comment it would seem like you felt it wouldn't be a problem.  Maybe I am doing something wrong.   

[G0HZU]

The original exam question involved relieving the ground under microstrip. Search for how many times microstrip gets a hit on this thread. Why are you (loosely) adding coplanar waveguide components to the simulation when this isn't necessary? Your circuit is just eating up memory for no reason.

I suspect it would be possible to do the microstrip simulation with just 1Mb memory with a little care.

[G0HZU]

If you want to move the goalposts to (grounded) CPW then try ditching the vias and then skinny up the box and just have a thin coplanar strip either side of the main signal trace and make sure the two CPW traces extend to the walls of the box.

[joeqsmith]

The original exam question involved relieving the ground under microstrip. Search for how many times microstrip gets a hit on this thread.  Why are you (loosely) adding coplanar waveguide components to the simulation when this isn't necessary? Your circuit is just eating up memory for no reason.

I suspect it would be possible to do the microstrip simulation with just 1Mb memory with a little care.

If you want to move the goalposts to (grounded) CPW then try ditching the vias and then skinny up the box and just have a thin coplanar strip either side of the main signal trace and make sure the two CPW traces extend to the walls of the box.

I suspect there was a bit of miscommunication was all.  If you take the time to go back and read the first couple of posts in this thread, while the OP was certainly proposing microstrip,  I talk about using a coplanar design.  I show pictures of the test boards and provide dimensions for the design.  I have not changed to a coplanar design, rather it was that way from the start.     

It seems it wasn't clear to you that the goal was to see how a simulation would compare with the physical hardware.   Certainly hardware could be built based on the limitations of the simulator but my intent has always been to simulate an existing design.    You wrote early on about the choice of using that ATC device.  I suspect that you failed to understand that a test board had already been built up with one from a prior experiment.   

If you would like to simulate what the OP had first proposed using the microstrips and capacitors, again I welcome seeing a parallel effort. 

[G0HZU]

You probably can still include vias and GCPW and keep within the 32Mb limit. You seem to be adding too many ports which will be wasting memory for one thing. Also there are various ways to reduce the memory requirements.

Learn to use the tool before giving up on it so soon. However, I suspect your mind is already made up and I think I know how this movie will end no matter how much I try and help you.

[G0HZU]

Try making the layout symmetrical and try playing with coarse meshing. There are other memory saving tricks as well. I don't think you need to add ports to the lower layer in this case (1.5GHz) as the bottom layer is grounded along the sides of the box and you can float it close to the box GND. This will save some memory.

[MartinL]

When I last looked at Sonnet Lite, you couldn't simulate a two-port GCPW board, because modeling one actually requires 6 ports in the simulation (at each end of the board you need ground-signal-ground: 3 ports). The Lite version only gives you 4 ports. So you can model a two-port or even four-port board if you use microstrip feeds, but only a one-port one with GCPW.