Analog I/Q demodulator vs ADC and digital I/Q demodulator

[prutser]

I am trying to find out the pros and cons for and SDR platform.  Suppose I have a frontend with an I/F of approx. 30MHz and like to have a IF bandwidth of 10MHz with demodulation handled in an FPGA.
 
There are 2 options:

- Use an IQ demodulator and separate ADC's for I and Q ( can be lower fs )
- Use a single DAC @ fs 65 - 80MHz and use a DDS with multiplier inside the FPGA for IQ demodulation.

I wonder of there are any clear pros and cons for both approaches and why ?

[Gregory]

Hello man, here some pros and cons

Analog IQ demo
   - less power consumption in the DSP/FPGA because lower clk
   - less expensive ADCs but need two of them
   - will have more IQ imbalance
   - for low SNR or high eye performance will need digital IQ crosstalk/imbalance correction algorithm
   - will need two antialiasing low pass filters (that will increase IQ imbalance)

Digital IQ
   - perfect mathematical assumption of demodulation (perfect mixer multiplication, "no" mixer harmonics, higher TOI)
   - will need higher clk FPGA and ADC
   - needs high dynamic range ADC
   - IQ lowpass filters after mixer will be digital FIR filters (a lot of multiplication or DSP slices needed)
   - will need one steep low pass anti aliasing filter at ADC input

In the digital IQ you can use nyquist subsampling / sampling down conversion to reduce the sampling rate needed.
If your signal is centered at 30MHz and have a 10MHz bandwidth, you actually need only a 20MegSample ADC.

The ADC needs to have 30MHz of analog bandwidth, but the sampling rate needs to be only double the bandwidth of the signal.

Sampling will down covert the signal for you (as sampling is very similar to mixing), in this case the aliasing will be your friend!

[radiolistener]

There are 2 options:

- Use an IQ demodulator and separate ADC's for I and Q ( can be lower fs )
- Use a single DAC @ fs 65 - 80MHz and use a DDS with multiplier inside the FPGA for IQ demodulation.

I wonder of there are any clear pros and cons for both approaches and why ?

analog pros:
- cheap
- simple
- low power consumption

analog cons:
- imbalance issues
- distortion issues
- temperature and age dependency issue
- component quality dependency issue

digital pros:
- low imbalance
- low distortion
- no temperature and age dependency
- no component quality dependency (except ADC)

digital cons:
- expensive (needs expensive FPGA and high speed/high dynamic range ADC)
- complexity (needs to develop verilog code to describe all math for signal processing)
- high power consumption (high speed FPGA and high speed ADC consume a lot of current)

In your case analog IQ demodulator will suffers from imbalance and physical differences between I and Q path. You will not be able to build ideally equals circuits for both channels. Also you will be limited with filters, because it's very hard and even impossible to build and tune good analog filter which can be comparable with good digital filter. But on the other hand, analog solution will be more energy efficient.

[A.Z.]

I am trying to find out the pros and cons for and SDR platform.  Suppose I have a frontend with an I/F of approx. 30MHz and like to have a IF bandwidth of 10MHz with demodulation handled in an FPGA.

as for the pros and cons, I believe the others already gave you extensive informations, I would just try giving you an alternative idea to the FPGA you're emvisioning, that is, the one described here

https://circuitsalad.com/2015/06/19/comming-soon-stand-alone-software-defined-radio-baseband-demodulator-no-computer-required/

the circuit, from Ray Ring uses a Spin Semi FV-1 IC which integrates 24 bits ADCs and DACs and, being programmable, is also used for demodulation

http://www.experimentalnoize.com/product_FV-1.php

so I believe that if you're designing an SDR, it may be worth a look; also, in its simplest form, an SDR based on the FV-1 may use (e.g.) an RT820... or an E4000 as the RF front end

[edit]

this stuff may be interesting too

https://www.maximintegrated.com/en/products/analog/data-converters/analog-to-digital-converters.html?utm_source=GoogleAds&utm_campaign=brand-analog-brand-adc&s_kwcid=AL!8732!3!376211791569!b!!g!!maxim%20adc&gclid=CjwKCAiAsaOBBhA4EiwAo0_AnLk6IC_a_WisXoeGVn9K7q_gytsZfToZFp4XijpLgT4eLtiiXhxPiRoC6P0QAvD_BwE

not the cheapest, but a 24 bits ADC would offer a pretty good dynamic range

 

[prutser]

Thanks for all the information. 

The FV-1 is an interesting IC, I'll keep it in mind. Basically I am looking for best possible quality, so probably I'll got for the all  digital FPGA solution. Modern
FPGAs have quite some multipliers, so I expect for only Mixer, CIC decimator and baseband filter the price of the FPGA still can be reasonable.
It avoids indeed all kind of imbalance issues.

[ejeffrey]

IMO if you are going to have a reasonably powerful FPGA anyway direct IF digitization is a no brainer.  The extra cost for the faster ADC is likely offset by avoiding the extra mixer stage and second baseband signal chain. If you are already doing FPGA development the complexity of a digital IQ mixer is pretty trivial.

If you are comparing a low power FPGA or even a microcontroller vs. a more powerful FPGA or you are very concerned about power consumption then it becomes more of a horse race where you have to look more closely at your requirements

Analog subsampling is probably the best of both worlds.  Power and cost will be competitive or better than IQ mixing and you will get the balance and analog simplicity of the direct IF conversion.  The downsides are that it is more conceptually complicated, requires more care in ADC selection and puts a considerably larger burden on the IF filter since you can't count on the baseband filter or wide ADC bandwidth to clean things up.