An alternative to quartz filters.

[ejeffrey]

It is true, if you need that much resolution high speed 16 bit ADCs are expensive, although they don't need to be hundreds of dollars: LTC2160 is 16 bit @ 25 MHz is listed as $25 in volume on analog.com  2161 goes to 40 MHz which would give more headroom.  A 14- or 12- bit ADC would be cheaper.  ADS4142 is a 14 bit 65 MSPS converter from TI for $12.  Not exactly cheap but I would be surprised if a commutated filter is going to be much cheaper.

One big factor that I still haven't seen is how wide a bandwidth you need simultaneously active.  If you only have a few adjacent channels at a time with a signal bandwidth of <100 kHz you can do this with a heterodyne receiver using a much slower ADC (like 1 MS/s).  You then digitize that band and use DSP to separate the 3 kHz channels.  This also reduces the processing power you need for your DSP.  On the other hand if you need 2000 channels with 3 kHz spacing you would need the higher speed and more expensive ADC, but the cost of your analog filter bank would also be greater.

[mawyatt]

 Mike, thanks. I studied Texas, now I am studying Analog. There is no answer yet. Probably your option will be the only one.

Just about any low voltage small SMD (SOT-23 for example) NMOS device should work, just look for something with a moderate RDSon, low capacitance & gate charge, and acceptable switching speed. Digi-Key has many as do other suppliers, and they only cost a few cents each (<< than $0.05 at LCSC), so not expensive.

BTW are you trying to pick a 3KHz wide signal within a 4KHz channel from a 3 to 10MHz span? Maybe multiple channels simultaneously?

Best,

[T3sl4co1l]

Uhh by the way, is that three-thermal NMOS, or integrated circuit NMOS?  It's rather annoying to make analog switches without a free substrate terminal...

(Which are still available, very few of them.  Good luck?)

There's still JFETs of course, if you don't mind the negative bias and relatively large drive required.

Or PHEMTs, more expensive and much faster than necessary I suppose, but often don't have body diodes as such, so there's that.

Tim

[mawyatt]

Either 3 or 4 terminals works. With 3 terminal you'll need to DC bias the input/output, with substrate connection you can pull the substrate below ground. When doing these analog switches on an IC we usually went with triple-well devices (if the process supported such) which allowed the selective bias of the various wells to achieve the optimal switch linearity performance.

At one point long ago we looked very seriously at doing the PolyPhase Mixers (PPM) switches in GaN, but the integration levels weren't acceptable at that time and we couldn't integrate the necessary baseband and logic, so shelved the concept. Later when we revisited this and did more analysis, we found that GaN couldn't outperform the NMOS switches for the intended PPM application. I'm not sure any semiconductor technology today can outperform a FinFET NMOS switch, unless your application needs very high standoff voltages, then GaN would be the likely candidate. We knew what 14nm FinFET NMOS could do over 10 years ago, and can imagine what 5nm or 3nm can accomplish today

Of course design cost have also skyrocketed from over $200M for 7nm, to over $400M for 5nm, so only massive chip quantities can ROI for this type of design cost investment, which probably only Smart Phones & iPads can generate

Best,

[T3sl4co1l]

Well sure it needs to be biased, but I mean, if the input is lesser than the output, body diode current flows...

Unless, do you mean bias between input and output, so that the signal itself is a chopped current ("pulsed DC")?  Hmm, the DC offset doesn't matter (almost trivial to filter out), and as long as the clock is stable (and since it's coming from a counter of some sort, duty cycle should be pretty consistent between phases, barring unlucky subharmonics?) it's not going to add anything to the output.  I suppose charge injection isn't a big deal either, mainly because of the filtering and symmetry?

At one point long ago we looked very seriously at doing the PolyPhase Mixers (PPM) switches in GaN, but the integration levels weren't acceptable at that time and we couldn't integrate the necessary baseband and logic, so shelved the concept.
...
Of course design cost have also skyrocketed from over $200M for 7nm, to over $400M for 5nm, so only massive chip quantities can ROI for this type of design cost investment, which probably only Smart Phones & iPads can generate

Yeeeah, that's my point... realize the audience you're talking to: there aren't many chip designers here.  If you're expecting applications, expect to see them in the crustiest damn NMOS money can barely buy.  Like, 2N7002 crusty.  So, I'm wondering if anyone interested enough to build one of these things, should maybe consider something a little fancier than that?  Because they're probably not going to be buying a wafer of 3nm FinFETs, as you note.

Even among nice NMOS, there isn't that much available.  It's not like you can get 200nm NFETs all by themselves.  There's no such thing as...an unbuffered "74LVC1G05"?  RUM001L02T2CL is one of the nicer discretes I know of, then after that you're looking at boutique arrays (there are some with Vgs(th) = 0, or "programmable", etc.), RF parts ($ $ $), or wide bandgap -- of which GaAs and GaN are traditionally RF parts ($ $ $ $), but their relatively recent entry to power switching makes them a little more attractive ($ $) for certain logic and signal applications as well.

Tim

[mawyatt]

 -- of which GaAs and GaN are traditionally RF parts ($ $ $ $), but their relatively recent entry to power switching makes them a little more attractive ($ $) for certain logic and signal applications as well.

Tim

We looked into combining the Switching Mode and RF together with a composite device of GaN and SiGe and/or CMOS called the GaNsistor, and another which was called Direct Digital to Antenna (DD2A). Worked on this long ago and was granted a couple patents on such, first was a 3 terminal Cascode type device that had a bipolar (or CMOS) input and GaN output (patent 7399857), then the DD2A was developed which could produce an RF power waveform directly at the antenna port based upon a digital input (patent 7903016). Later others utilized the GaNsistor concept with Depletion Mode MOS in place of the GaN for use in high voltage power switching applications.

A very clever rendition of the DD2A utilized a sequence of these DD2As in a traveling wave arrangement which allowed the power to build as the RF wavefront progressed towards the antenna port, in addition the resolution also increased as the wavefront progressed. A highly successful DARPA program called Power DAC emerged from this concept

Best,

[mawyatt]

Well sure it needs to be biased, but I mean, if the input is lesser than the output, body diode current flows...

Unless, do you mean bias between input and output, so that the signal itself is a chopped current ("pulsed DC")?  Hmm, the DC offset doesn't matter (almost trivial to filter out), and as long as the clock is stable (and since it's coming from a counter of some sort, duty cycle should be pretty consistent between phases, barring unlucky subharmonics?) it's not going to add anything to the output.  I suppose charge injection isn't a big deal either, mainly because of the filtering and symmetry?

Tim

This is for bandpass use so the input and output can be AC coupled, a simple series C is all that's required if the input or output has a DC bias. This has is no DC chopping or body diode current flowing. Without access to the NMOS body in a 3 terminal device then you can DC bias the NMOS channel if the input signal is expected to be high enough to slightly forward bias the body diode.

You actually only need to apply the bias to the input or output, since they are directly sequentially DC coupled thru the NMOS channel and series R. All the capacitors will quickly assume the proper DC level and no differential DC will exist between input and output, nor between individual capacitors....unless you have some really bad leakage in the caps or switches 

Best,

[mawyatt]

Yeeeah, that's my point... realize the audience you're talking to: there aren't many chip designers here.  If you're expecting applications, expect to see them in the crustiest damn NMOS money can barely buy.  Like, 2N7002 crusty.  So, I'm wondering if anyone interested enough to build one of these things, should maybe consider something a little fancier than that?  Because they're probably not going to be buying a wafer of 3nm FinFETs, as you note.

Tim

The crusty old 2N7002, with a 1.32K resistor and 0.01uF COG chip cap (or 132 ohm R and 0.1uF cap), an 8 bit shift register (74AC164 or 595), and you are good to go for an initial test breadboard setup with an 8 phase version and total cost less than $1.

Sure there are better NMOS devices than the 2N7002, and faster shift registers than the 164, but these are available and cheap. This should yield a ~3KHz BW that was mentioned in the 3~10MHz frequency range with an 8X clock, and it's easy to build a breadboard with just 8 NMOS, R and Cs with a single 74AC164 chip 

Think this fits your mentioned audience and application quite well indeed

Best,

[MikeP]

 I was late for an interesting conversation.

 16 bit ADCs were mentioned above due to the need to have a range of 80 dB. In reality, this will not happen even with 16 bits. The sampling rate for 10 MHz cannot be 25MS or even 65MS. The filter we are talking about will sample at a frequency of up to 100 MHz. And this is not enough.

  It's hard for me to explain this, and I'm probably grossly mistaken, but with heterodyning we introduce a number of undesirable factors. As a result, it will be even more difficult to select the desired bands. Correct me please. Finally, the bands are not 2000, there are less than ten. Among other things, the phase that can be lost is important here. Unfortunately, this moment is still not very clear to me.

[MikeP]

 Further. I never found anything suitable from the IC. The study of small transistors yielded results. It turned out that there are quite a few similar items. Here are some examples of the smallest ones.
  Finally about the body diode. It seems to me that it can open. If we use large signal amplitudes.

[RoGeorge]

Not sure about others, but for me this topic sprouted to an interesting subject I didn't know before:

The Polyphase Mixer, or maybe the N-Path Mixer, don't know what the proper name is, brought to attention by mawyatt.

Just started looking into this kind of mixer, and have some question and some personal misunderstandings to ask, also want to subscribe to this thread

Should we have a new topic about this switched type of filter, or should I just start shooting questions here, with the risk of totally derailing, or maybe helping, this topic IDK?

[mawyatt]

We coined the name PolyPhase Mixer, academia uses N-Path Mixer, later DARPA came up with Mixer First, all are correct.

Many will view this mixer as just a simple Bi-Phase passive mixer with the diodes replaced with NMOS switches like some of the older JFET applications, or maybe just adding more phases. However, the more time you spend researching actually how this PPM works, the more you begin to understand the totally different behavior and performance of the PPM vs. a passive Bi-Phase mixer. The more you begin to understand the more you realize you don't actually know what's really going on in detail, so this becomes a very deep dive into the core behavior of frequency mixing and translation and why it so quickly caught on with worldwide academia and spawned 100's of scientific papers, dissertations, and thesis on the subject.

This first clue that this is something totally new, untouched and special is the better than theoretical noise performance for a passive mixer 

Had asked earlier about starting a separate thread so we don't divert MikeP's filter interests. If you want to start another thread on PolyPhase or N-Path Mixers I'll be happy to contribute the best I can.

Best,

[MikeP]

 Indeed, we should not mix the filter and mixer. It will be much more comfortable for readers in the future. Thus I offer to Mike to create the appropriate thread. I will try to change the name of this thread with the words + Switching Filter. But it seems to me that the name cannot be changed.

 About the conductivity of the diode in MOSFET. Here is a simulation with an input voltage of 2Vp-p. The switch (red line) accepts all input voltage. This is a differential measurement. These are obvious things. Now I have done some experiments. Unfortunately, I was able to shift only the input section of the switches.

[DC1MC]

OK, this really got my curiosity, I was wondering if this filter can be used in a transcevier instead of a crystal filter.

The IF is 8.251MHz and the modulation is SSB and CW, for SSB one needs a bw of 2-3KHz and for CW 250-500Hz.

I think I can place 16 transistors and the rest on a PCB suitable to be placed on the filter connector, the question is how will such a switch look,how do you bias it in regard with the R/C filter, does it need a low impedance on the input of the R/C network, any prctical schematic will be appreciated, epay sells in DE 30 pcs. for 3EUR and the other compents costs are marginal, but I have no clue how to bias these MOSFETs in this configuration, but I'll love to wipe out quickly a prototype and test it.

 Many thanks,
 DC1MC

[mawyatt]

My work with this dates back 40 years, so memory isn't so good

For replacing the IF filter look at the harmonic content and how this will impact the IF and interact with the LO, this will help decide the number of sections which can be even or add values. For the different bandwidths look to switch in a shunt cap for the lower BW, you could change the R but that's more difficult because it "floats". The bias will depend on many factors but the filter can be AC coupled as mentioned so you can just have a large resistor feeding the input after the AC coupling and adjust the bias voltage for the best response.

WRT to the impedances that's something you'll have to play around with, obviously higher Rs yield higher effective filter impedances with smaller caps. So a tradeoff between I.L. and attenuation will likely be required.

Of course you can "tune" this filter center frequency with the clock, so it's possible to forgo the receiver heterodyne all together and place the filter right at the input RF frequency, this is what we did long ago. This allowed us to bounce around a wide frequency range and look for 10Hz wide signaling tones that were at specified absolute frequencies.

Have fun and report your progress and findings.

Best, 

[gf]

MikeP's requirement are 80dB stop band attenuation at 7.5kHz bandwidth, while the -3dB passband should still be as wide as 3kHz. At the baseband, a corresponding lowpass would need to be a high-order Butterworth or Chebyshev filter, in order to achieve this amount of passband flatness and transition band steepness. Is the proposed commutating/polyphase filter able to provide a frequency response with the required squareness ratio? At the baseband, it seems to be a first-oder RC filter only? Or did I miss anything? [ If the filters in each of the N paths would need to be replaced by a (say) 10th order Butterworth in order to fulfill the requirements then the simplicity of the design were gone. ]

How much harmonic rejection can be expected from the proposed polyphase filter, assuming realistic tolerances of components and timing? Since the band of interest is 3..10MHz, at least the 2nd and 3rd harmonic need to be suppressed, when tuned to e.g. 3MHz. And 80dB out of band attenuation are the minimum required by MikeP. Is this realistically achievable in practice?

[mawyatt]

The basic commutating filter is a 1st order passive RC low pass translated around the commutating clock frequency/N as discussed in the simple schematic shown previously. About 10 years ago USC did some work on translating a more complex bi-quadradic impedance up to the antenna port with the PolyPhase Mixer, but this was not a true bandpass filter (was a mixer) as being discussed here. As mentioned, my work was ~40 years ago and I haven't kept up with this topic and what levels of performance are achievable. The OP found an interesting thesis from 2012 which might be worthwhile to review for those interested, but I haven't had the time to do so. 

I'm sure multi-order responses can be achieved but don't know what's been done to date. This is where some investigative research needs to be performed by those interested, although I doubt a 10th order Chebyshev or Butterworth could practically be achieved.

This commutating filter is so simple and cheap to get started with, some hands on might be useful for those interested, wish I had the time for this but that's not going to happen.

Hopefully some folks will play around with these filters and post what they've found.

Best,

[T3sl4co1l]

So, what is the significance of the number of taps?  I don't think I've seen that discussed here yet but I admit I haven't been following along with the citations referenced.  Is that like a sinc sidebands thing (like a N-tap boxcar filter)? Does it work just fine with 2, in which case why go to 8 at all?  Is there something magic about 8, why not 16, etc.?

Tim

[mawyatt]

I'm not the inventor of this type filter, just a user some 40 years ago that adapted it's use with available devices then, and reported it here as a possible consideration for the OP use which may or may not be acceptable performance-wise.

Think you need to spend some time reading and researching the mentioned references (and their references). If you spend some time digging I'm sure you'll find the answers to your questions.

Edit: BTW the origins of this Commutating Filter date back into the 1960s, but I can't remember the reference. In the paper (probably IRE) the commutators were car distributors and a synchronous motor drove the commutators as the clock, in ~1980 we replaced the distributors with fast (then) NMOS devices and the motor with a low jitter high speed programmable clock generator.

Best,   

[gf]

So, what is the significance of the number of taps?  I don't think I've seen that discussed here yet but I admit I haven't been following along with the citations referenced.  Is that like a sinc sidebands thing (like a N-tap boxcar filter)? Does it work just fine with 2, in which case why go to 8 at all?  Is there something magic about 8, why not 16, etc.?

I browsed very briefly through a couple of papers. An important aspect of polyphase mixing seems to be image suppression, i.e. the cancellation of input frequency bands at the first few harmonics of the LO frequency, which were otherwise down-mixed to the baseband as well if the LO is not a pure sine wave and the mixer is not a perfect multiplier (which is not granted at all for e.g. switch-based mixers).

How is that related to the commutating filter? It was not obvious to me either, at the first glace, that the simple switch-R-C-switch combination eventually acts as down-mixer -> RC lowpass -> up-mixer, thus transforming the RC lowpass into a bandpass centered at the LO frequency - but with side-effects. Without cancellation of LO harmonics, each band at i * f_LO were eventually down-mixed to baseband, and then the sum of all these images (at baseband) were up-mixed to to all bands at j * f_LO (where i and j are integers >= 1). Again, the polyphase approach can obviously cancel undesired images, at least for a couple of LO harmonics (depending on the number of paths).

[ That's at least my understanding of what I did read so far... ]

[T3sl4co1l]

I read much of the BSTJ paper.  They give two typical applications: a delay line (probably of interest as delay matching has always been a huge concern for Bell?), and a particularly high "Q" filter.

The delay is pretty ordinary, as from our perspective it's simply a macroscopic BBD, or an analog (continuous voltage, discrete time -- switched capacitor) circular buffer.  Not bad for 1960, though doing it via mechanical means is kind of barbaric, even for them (but hey, transistors were still expensive back then).  The circuit used is perhaps a bit unexpected: they go through the derivation of the impedance of a single all-capacitor switch, showing it has the characteristic of a stub transmission line, with leakage resistance equivalent to termination resistance.  The implementation of a delay is then obvious: put it in a feedback network.

The bandpass filter was implemented with diode gates and transistor multivibrators, running at 25kHz.  They give N = 4 (so, operating in quadrature -- they give a note earlier (p.1328) that two channels are possible given this condition, which makes sense as half the channels here are essentially complementary), though a full circuit isn't given (presumably the diode gates are decoded one-hot, as Fig.10's switches suggest, in which case d1 = d2 ~= T/4).  They don't show how bad the sidebands are, but it's clear that it won't be great: N is small.  N seems to give the sampling ratio, as we expect from ordinary/modern DSP work.  So, larger N simply affords a larger ratio between passband and stopband, and antialias filters are required in the usual way.

A downside: at high frequencies, we may find no choice but to use a pile of PLLs to generate the phases.  For example, say we want an 8-path filter centered at 144MHz.  Well, we need Fclk = 8*144MHz to use an 8-way counter-decoder here.  Possible, certainly, but well beyond the reach of average 74HC logic.  Well, 144MHz itself isn't exactly in HC bandwidth either... maybe not a great example, but you can see there's plenty of range where a given logic family might be suitable, but for the master clock frequency required, or the pulse width demands.

I wonder what you'd use for that, actually; maybe ECL, and just (schottky) diode gates, and make sure the signal amplitude is low enough to avoid bleed-through?  So, we'd just get whatever dynamic range we get that way.  74LVC I don't think is quite fast enough for that, but it would be close?  The uh, whatever the next lowest voltage, newest CMOS family is after that one I forget, would probably do.  For sure, an IC would be able to pull this off, netting say a volt or two of dynamic range, and clean (NMOS or other) switching.

As for smooth LO input (p(t) and q(t) being sinusoidal, or nearly so), it seems it doesn't give images; which makes sense, it's essentially a baseband quadrature (or more) receiver.  If only it were easier to perform highly [bi]linear mixing...

Tim

[mawyatt]

In our rendition back in ~1980 we used the fastest ECL available for the 8 phase clock generator which allowed coverage of the frequency bands of interest. 8 phases were selected to move the switching harmonics to where they weren't an issue and allow simple pre-filtering. We never did integrate this filter, other things came along with a new developed PLL (later patented 4904958 & 4912334), but it did work quite well for the intended purpose of detecting signaling tones with a post log amp. Had we continued with the development and integratation, maybe realizing the PolyPhase Mixer as a derivative of this commutating filter sooner than later by over 20 years

Best,

 

[mawyatt]

Further. I never found anything suitable from the IC. The study of small transistors yielded results. It turned out that there are quite a few similar items. Here are some examples of the smallest ones.
  Finally about the body diode. It seems to me that it can open. If we use large signal amplitudes.

The JFET is too weak to consider, you want something with a much higher IDSS so you'll get a lower RDSon, the NMOS device seems like a good switch candidate tho.

Best,

[MikeP]

 The use of discrete transistors entails a number of inconveniences. Including poorly predictable offset. Therefore, I hope that an integral solution is possible.
 The FSA3157 turned out to be a very popular solution in the RF field. There are similar things.

 SN74CBTLV3126 is my find today. Or FSA1259. They are very fast switches, in very small packages, with very low resistance. Logic control levels and signal amplitude up to 3 volts. At least a good option for experimenting. Or discrete transistors preferable?

 Let me ask you a question. It seems to me that the stability of the local oscillator is very important. This can be done without much difficulty - there are now many programmable oscillators. My single experience confirms the possibility of this solution. The next link is the logical generator of control signals - shift registers or counters or... I want to create a ten-stage filter. Can I get recommendations?

 Thanks.

 

[gf]

@MikeP, I'm just wondering whether your requirement

... has a bandwidth of 3kHz (-3dB) and 7.5kHz (-80dB).

is still a mandatory criterion? That's a quite challenging slope of about 60dB/octave!

How do you think to reach this goal with a first oder passive commutator filter, having a slope of only about 6dB/octave

[ I.e. if you manage to achieve -80dB @7.5kHz, then the -3dB passband were only ~300Hz instead of 3kHz.
Or if you make the passband 3kHz then the rejection at 7.5kHz were only ~10dB.
You simply can't achieve both with a first order filter. ]

No offence meant - I just try to keep an eye on the requirements you did specify originally.