50 Ohm Characteristic Impedance Traces from OSH Park

[ihunter2839]

Hello,

First off, this is my first post but I am a long time lurker - thanks to Dave for the site and to all the contributors who make this place what it is!

Now, my problem... I am attempting to make a 2.45GHz RF amplifier using the Qorvo TQL9093 chip. I have designed and manufactured a 4 layer board through OSH using the controlled impedance parameters listed here https://docs.oshpark.com/resources/four-layer-impedence-table.png. This is not my first attempt (and failure) at making an RF amplifier board, so I've added a through calibration trace with two DC blocking caps to test the trace's performance. Using my NanoVNA, I am measuring a return loss of 4-5dB when terminating the through calibration line with a 50 Ohm load, which (if my math is correct) suggests a characteristic impedance of roughly 170 Ohms (!).

Some notes on the board design / what I have considered when designing it -

1) The controlled impedance trace is a microstrip routed on layer 1. Layers 2, 3, and 4 are all solid ground pours.
2) There is a ground pour on the top later, but it has been pulled back from the microstrip trace by a distance that is roughly 6 times the trace width (15mil trace, 100mil spacing to ground pour)
3) The ground pour and internal / bottom layer are stitched together with vias. Vias have been spaced with a distance less than 1/10th the wavelength to avoid resonances.
4) The DC blocking caps on the lines are 100pF, C0G/NPO 0402s.
5) I've taken the stackup information provided for OSH's 4 layer boards and plugged them into Altium's impedance calculator, and it is in agreement that a 15mil trace should provide a 50 Ohm characteristic impedance.

I've attached the board and schematic files (for Eagle 7.5) - if there is some other file format that is easier for folks to access, let me know and I will try to generate it! Any suggestions, ideas, or insights into what I am doing so horribly wrong are greatly appreciated, as I've exhausted all the potential issues that I am currently aware of.

Cheers,

Ian

Edit - added a .png of the board so folks can see it without having to pull down the zip file.

Edit 2 - added smith chart and return loss plots from my NanoVNA when terminating into a 50 Ohm load.

[fourfathom]

I have heard of people putting a partial ground-relief under the SMA center-conductor pad, since the fat footprint will otherwise causes a low-impedance bump.  I don't know if this is your issue (especially since you are measuring a high impedance rather than a low one).  I use SMAs a lot on my RF designs, but these are all sub-100 MHz so I don't worry much about impedance control.

Can you show a frequency plot of the impedance (Smith chart, or R/X chart)?  With the right trace length a low-Z can be transformed to a high-Z.

Somebody who knows this stuff better than I will probably come along any time now...

[ihunter2839]

Fourfathom,

Thank you for your suggestion regarding the ground relief under the SMA center conductor - I will make that change on the next iteration of the board!

I've attached some relevant plots from the NanoVNA to the original post.

Cheers,

Ian

[fourfathom]

Fourfathom,

Thank you for your suggestion regarding the ground relief under the SMA center conductor - I will make that change on the next iteration of the board!

I've attached some relevant plots from the NanoVNA to the original post.

Cheers,

Ian

I'm much more comfortable in the MHz region, so I'm really over my head here...  I have no idea how much and where you would relieve the groundplane.  I suppose you could also make the pad narrower, but there are 3D aspects given the cylindrical connector pin.

What is your dielectric?  FR-4 or something more exotic?

I would be curious to see a broader frequency sweep -- that way we can understand the resonances affecting the impedance.  Assuming a 15cm/ns propagation velocity of FR4 microstrip ( found this via google), a 1/4-wave trace would be about 6.25 cm at 2.4 GHz.  This would transform a low-Z to a high-Z.  Your test trace doesn't look that long though.

Again, waiting for an expert to jump in!

[EggertEnjoyer123]

Your massive pads for the SMA connectors are probably what's causing issues. Also try extending the ground plane all the way to the edge.

Use a pair of calipers to measure the center pin of your SMA connector, and try to resize the pad to that width. If it's too large, you can ignore it and take the return loss hit, or you could look at removing the ground plane under the trace (which requires simulation). You could also buy a SMA connector with a thinner center pin (those tend to cost more).

Here's my quick and dirty guess as to what your setup looks like. The pad looks more than 4x thicker than the 50 ohm trace, so the impedance is probably at least sqrt(4) times lower (I guessed 20). All the lengths are guessed and multiplied by 1.5 to compensate for the fact that signals in FR4 travel about 2/3 as fast as signals in air. The result is -7 dB S11 (my guess is probably somewhat off). If you reduce the width to 2x the 50 ohm, then the impedance would be approximately 50/sqrt(2), and that leads to -19dB S11 in my calculation which is definitely good enough. The standard edge connector definitely could fit in that width.

[radar_macgyver]

You could grab the free version of Sonnet and simulate the structure to find out how much of the plane to remove. I found that for a 4-layer board, L1-L3 under the pad can be made roughly equivalent to the impedance for L1-L2 under the microstrip or CPWG. Attached is my simulation result, the S11 was better than -20 dB over the frequency of interest.

[selcuk]

The design of the pads of those SMA connectors are tricky. So you may want to use a EM field solver as suggested in the previous post. Take a look at this detailed project. He used openEMS for the simulation:

https://github.com/toammann/Multilayer_SMA2Microstrip

What is the part number of 100pF capacitors?

[tggzzz]

Random thoughts, worth what you paid for them...

How accurate is the impedance of the line itself?
What do/don't OSHPark guarantee?
What about FR4/pre-preg manufacturing tolerances?

Does your NanoVNA have sufficiently high frequencies that an inverse-FFT could give some insight about the impedance as a function of distance?

[ihunter2839]

Thank you all for your suggestions and input!

After seeing EggertEnjoyer123 and selcuk's suggestions that it might be related to the SMA center conductor pad, I realized that I hadn't looked at the datasheet for the edge launch connector I am using for quite some time https://www.digikey.com/en/products/detail/cinch-connectivity-solutions-johnson/142-0701-801/35280. Sure enough, there is a section that explicitly mentions that the pad size needs to be tweaked to achieve the desired return loss for a given stackup that I had previously overlooked!

As a quick and dirty test, I took one of the boards to the band saw and cut away the oversized pads and soldered the center conductor directly to the microstrip, and whalla! It's not perfect, but -15dB return loss is certainly a whole lot better than -4dB return loss....

I think my next steps are re-reading the datasheet and trying the recommended pad dimensions with a 2 layer FR4 board. I am under the impression that the microstrip trace with a standard FR4 core is too wide to integrate with smaller RF ICs, but it would be good to get a baseline of performance and iterate from there.

@EggertEnjoyer123 - what program are you using to simulate the lengths of transmission lines? I have been playing with SimSmith but whatever you are using looks like it would be worth playing with as well.

@radar_macgyver - I have the free version of Sonnet installed, now I just have to learn to use it 

@selcuk - caps are these, I think they should be acceptable? https://www.digikey.com/en/products/detail/yageo/CC0402JRNPO9BN101/302758

@tggzzz - OSH table suggests their tolerance is +-5 Ohms for a 50 Ohm target, and after talking with their support I believe that figure is based on their best estimates of the dielectric manufacturing tolerances. Re: an inverse FFT, my unit operates from 0 to 3GHz - I am not sure whether this would be sufficient for the purposes of what you are suggesting.

Thank you all again for your input - I was at a dead end but this has been refreshing! In hindsight it feels like it should have been pretty obvious... I still have an awful lot to learn in this black magic world of RF.

Cheers,

Ian

[tggzzz]

@tggzzz - OSH table suggests their tolerance is +-5 Ohms for a 50 Ohm target, and after talking with their support I believe that figure is based on their best estimates of the dielectric manufacturing tolerances. Re: an inverse FFT, my unit operates from 0 to 3GHz - I am not sure whether this would be sufficient for the purposes of what you are suggesting.

1.5GHz manages 4cm resolution https://entertaininghacks.wordpress.com/2015/07/27/poor-mans-homebrew-tdr-with-4cm-resolution-part-1/ so 3GHz should be 2cm.

Why not try it and see; the NanoVNA has such a mode built in

[Gerhard_dk4xp]

we recently had a similar discussion on microcontroller.net.
Not OSH Park but JLCPCB 4 layer el cheapo process.
5 boards 100*100 mm for $6 or so, w/o impedance control option.
first version with standard SMA from the lib for 2-sided boards.
GND = layer 2, 3, 4 
You see the excessive capacitive local loading. Even the amount
of tin seems to matter.
Optimum microstrip for the JLCPCB process is 11.5 mil from
their simulator. I drew 12 mil.



the 2nd board has cutouts on layer 2 and 3. under the SMAs.
Otherwise GND on 2, 3, 4.



SMAs = Rosenberger, with narrower inner pin above the board.
The microstrip is between time divisions 7 & 8.
The SMA is slightly overcompensated. (the tiny peaks)
I made the ustrip 10 mil wide IIRC to see if I can escape a BGA.
There are also some fancy corners that do not seem to be show stoppers.

Measurement setup:


top   =  layer1= red
GND = layer2 = blue
gnd = layer3 = orange
gnd = bottom = green

[Hamelec]

i think you own more than one PCB?
tune it - take a Dremel and, grind the width of the solder pad of the 50R line first and then the backside GND - always measuring what happens..

[rfclown]

Sounds like you are on track. I've used 14 mils for OSH Park 4 layer. I wouldn't use the 2 layer for the amp. Not only is the microstrip wide, but the board material isn't as controlled. The ISOLA FR408-HR is decent.

Instead of field solvers, I just use microstrip calculators, which is where I get the 14 mils. When I've made a wider pad for a SMA pin, I calculated the necessary width based on the distance to layer 3 (or wherever the reference plane is). Usually I'm lazy and don't make a wider pad... just solder to the 14 mil line. But that's cuz I just use this for test boards that I'm hand soldering.

edit: if you do have a transition in ground reference plane to change the microstrip width, you want to have multiple vias near the transition so that the two ground reference planes are at the same potential.

Also OSH Park doesn't let the metal get to the edge of the board. I sand down the board edges where I have SMA side launches so that I don't have that gap by the connector.