KocsisV, I've been trying (again) passing variables to the Makefile.
It should be possible to declare them in the Environment (Under Properties... C/C++ Build).
It is possible to pass env variables, that's not the issue at all. (See the examples later.)
The issue is still the
when it gets executed and the what the eclipse internal
builder state is. I explained in this post why its not working:
https://www.eevblog.com/forum/reviews/stm32-oled-digital-soldering-station-for-t12-handle/msg4189318/#msg4189318To provide examples:
https://github.com/KocsisV/stm32_soldering_iron_controller/tree/d8783b6743ef06fe6ce97db9e0d481d5a00da460In this the code gen is called for each configuration separately -> it only runs for that specific hardware. It runs in the pre-build stage. The internal eclipse builder already generated the makefiles at this stage, it looked through the project and picked out the specified source files and include directories. Since the generated files were not yet present (assuming a clean build), the makefile what eclipse generated will not contain the generated files, and it is not possible to add them anymore. The targets are already "created".
To see where this is called: right click on the main project, properties, C/C++ Build, Settings, Build Steps tab, pre-build steps. This pre-build step is invoked by the already generated makefile.
It is also possible to extend the generated makefile by a "makefile.init" file in the project root but that basically achieves the same thing.
https://github.com/KocsisV/stm32_soldering_iron_controller/tree/49ad550da55d91a381d962cc7e79dcc9e60b1c65In this the code gen runs before eclipse creates its makefiles -> the generated files will be included in the build. The issue with this is that this builder only runs once, regardless if you ask it to build one configuration or all. And from the variables eclipse provides its not possible to determine if its trying to build a single configuration or all of them. So it works if you only build one configuration at a time, but not for build all.
To see where this is done: right click on the main project, properties, Builders, there I added a new builder named GenerateSources, click on that and on the right click edit. Here it can be specified when to run this builder, what to invoke, etc etc. On the tool arguments section you can see how I pass the "active configuration" into make.
https://github.com/KocsisV/stm32_soldering_iron_controller/tree/02f01120f2284c266f30d4d062747c54ba6679ffThis one is almost the same as the previous, difference is that instead of the main project containing the builder which runs before eclipse's internal builder's makefile generation, each target hardware project has its own builder. The issue similar to the previous, building one configuration works, building all does not. But it fails because of an entirety different reason: CDT bug not triggering the dependency's build.
To see where this is done: same as before, when you import the main project click "search for nested projects", then you will see a project for each hw target. Right click props... on the hw projects.
The main project depends on these hw projects, to see: open the properties of the main project, C/C++ General, Paths and Symbols, References tab. There you will see that each configuration refers to the required hardware project's other config.
clean :
ifeq ($(BOARD_TYPE), KSGER_V1_5)
As I said, don't use IFs
Forget that "IF" exists. Forget any and every conditional operator, loop, etc. Make is a declarative language, you don't define "code to run" you define targets and relationships between them. Construct the commands for a specific rule to depend on the target being built. See the current makefile
for codegen for example:
https://github.com/KocsisV/stm32_soldering_iron_controller/blob/updateProjectStructure/mcu/generate_sources.makefile. There is no "IF" in lines 24-29, yet it runs all the codegen. If in the future another hw target is added, these lines don't need to be changed at all, only the "all" target need to be modified with to add a new dependency, that the "all" target needs that new ./boards/XXXX/src/generated file. The rule between lines 24-29 will match this new name too.
So simply
clean : $(BOARD_TYPE)
then another target with the name KSGER_V1_5 in this case does the same as your if-elif chain. And the if-elif chain will not work in most cases anyways, due to make assumes its a single target, it does not know it depends on env vars (and it builds multiple targets) if you don't include it in the target name or dependencies. You can even get rid of the concrete target name completely by constructing the rule in a way that the name is used to select the target in all cases. Eg
clean_% :
... instructions to clean on on $* ($* will equal %) ...
(Btw don't do this "clean : $(BOARD_TYPE)" thing, because this has the same issue as having a single target conditionally building something, use "clean_$(BOARD_TYPE) : " instead.)
Please use spaces instead tabs.
Ups. I already have eclipse configured to use spaces instead of tabs (and display tabs as 2 spaces wide). Is there any in the PR you just merged, or is this only an issue in the makefiles?