Intronix Logicport 34 Channel Logic Analyzer Teardown

[amspire]

Following a discussion in thread https://www.eevblog.com/forum/index.php?topic=5361.msg70133#msg70133, here is a teardown of the Intronix Logicport 34 Channel Logic Analyzer.

The website is http://www.pctestinstruments.com

The wires look like they are good quality - perhaps teflon or similar.

Extra plug-wire assemblies cost about $39. The reason why you may get more connectors is that it makes it very easy to move the logic analyzer between projects.



The EZ-Hooks are not standard - they are an optional extra at a cost of $1.75 each.



The IC in the top left corner is a 93C46 serial EEPROM chip.





The input offset can be adjusted between -6v to 6v.

This is the approximate circuit used to vary this input offset voltage.

[alm]

Interesting that they use a passive circuit to set the threshold, I would have expected some sort of comparators. Does the FPGA have inputs with a threshold of around 0V?

[amspire]

I haven't looked up the Actel data, but it would be something above zero - perhaps half a volt.

That is why I said my circuit was approximate - I don't know the actual voltage changes on the 50K resistors.

Their approach seems to work as it can sync with an external clock up to 200MHz, and it can capture logic state at up to 500MHz using the internal clock.

It looks like they have done a reasonable job keeping all 34 track lengths to close to equal.

[alm]

So the offset voltage is probably slightly asymmetric (-2.2 to 1.8 V or so). They apparently use the ESD protection diodes to clip the negative part of the signal. Don't love the design, but I guess at the ~40k output resistance of the signal reduces the currents to fairly low levels, and apparently the recovery of the diodes is fast enough for their purpose.

[amspire]

I am sure the offset will be asymmetric as you suggest, but without looking at the Altera Cyclone data, it is just guesswork. Altera might even offer several input buffer options, and picking one would also be guesswork.

It seems they do overdrive the Altera inputs, and they must recover pretty fast, as you can apply up to a 15v p-p logic signal.

I think the fact that the input current is limited by 150K resistor or a 4.7pf cap in series with 370 ohms limits the energy going into the clipping diodes. So they can probably let every pin clip at the same time without pushing the Altera into dangerous territory.

They have been building these since 2006 and they are solid. The analyzers do what they say the will do.

[seattle]

I have one of these for FPGA work and they are indeed solid. The specs for FPGAs are generally that you can overdrive them as much as you wish AS LONG AS you respect the thermals. On Xilinx, for example, this means up to 10 mA can flow through the ESD diode. So, on a 10V input signal, this means a (10-3.3)/0.01 = 670 ohms and you are good on a single pin. If you wanted to do that on 100 pins you'd have to think a little more.

With the 150K resistor, they are at about 100uA steady state, which is about 2 orders of magnitude below the limit of the ESD diode (assuming Altera is similar to Xilinx). So it's safe.

Note, also, there is no ESD protection. The FPGA provides about 2 KV of inherent protection, and you have a about 370 ohms of series R to help a bit. But by and large it's just using the FPGA protection limits. Which is also fine, based on field experience.

[EEVblog]

The EZ-Hooks are optional? 
that really is quite pathetic!

Dave.

[aparlett]

The EZ-Hooks are not standard - they are an optional extra at a cost of $1.75 each.

that's a joke,the amount of time wasted playing with that thing would kill any money you saved

[amspire]

The EZ-Hooks are not standard - they are an optional extra at a cost of $1.75 each.

that's a joke,the amount of time wasted playing with that thing would kill any money you saved

When it came out about 5 years ago, it was a bargain compared to the alternatives.

Other then some PC software updates, it has not changed since then.

In terms of an analyzer that is fast, reliable, lots of ports, that has PC software that actually works, and that does most of the important tasks in the hardware rather then the computer, it is hard to find something better and cheaper.

Everyone has had over 5 years to make something better and cheaper. No-one has quite done it yet.

Richard

[codeboy2k]

The EZ-Hooks are not standard - they are an optional extra at a cost of $1.75 each.

that's a joke,the amount of time wasted playing with that thing would kill any money you saved

 [...]
In terms of an analyzer that is fast, reliable, lots of ports, that has PC software that actually works, and that does most of the important tasks in the hardware rather then the computer, it is hard to find something better and cheaper.
  [...]
Richard

I have to agree with Richard.  I've owned mine about 4 years now, and it's never failed, and is extremely reliable and the software always works like it's supposed to . 
It has extensive hardware triggering, and I only wish it had more memory, then I could make my triggers simpler. As it is, and for the price, it's a great piece of hardware.

I look at some of the cheaper ones that come out today, and I think they are more of a joke than this one is, with no input protection, not enough inputs, a slower sample rate, etc.

I'm very happy with mine.

[zzg]

Hello,

Sorry for raising a somewhat old topic. I'm trying to understand how the LogicPort input circuitry works. Unfortunately, not everything is clear to me. I have two questions:

1) Why there is no ESD protection for 4.7pF capacitor? In case of ESD discharge such a small capacitor will be charged to most of the ESD voltage (could be few thousands of volts). Maximum allowed voltage for capacitors of this value and this size (0603 package) usually is no more then 500V. It's quite probably that the capacitor will be damaged as a result of ESD discharge. Am I wrong? May be I'm missing something?

2) Could someone clarify the purpose of 100 Ohm resistors before FPGA inputs? Why instead of having 270 and 100 Ohm resistors in series they are not replaced with just one resistor of 370 Ohm. My guess, the purpose of 100 Ohm resistors is related to signal integrity. Indeed the trace before 100 Ohm res is quite long (6.5 cm). Such a trace is a transmission line with a total inductance about 20nH and total capacitance 2.7pF (approximate guess). Maybe 100 Ohm resistors are used to prevent from terminating this transmission line directly to FPGA pin capacitance (6pF). So these resistors actually reduce ringing on FPGA inputs. However, I'm not absolutely sure. Can someone explain this issue?

Thanks.

[amspire]

When you see an input circuit like the one Intronix used for the voltage offset, you know that it was designed by by some poor engineer who spent a month or two juggling with board layouts, resistor values and resistor configurations until the best overall performance was achieved. You know they spent a lot of time on this as getting the signal from the test board to the Altera input pins with the offset adjustment is the most critical part of the hardware design. The Logicport can work at higher frequencies then most of their competitors, and this input circuit and board layout is the key.

I would say the resistors at each end of the transmission lines are there to dampen ringing, but I couldn't tell you if the motivation for the 100 ohms was for better signal integrity on the input pins,  limiting the peak current into the Altera input protection diodes to a level that allows the diodes to recover in nanoseconds even with transmission lines that are not properly terminated, or just to stop the transmission lines ringing like a bell. In circuits like this, you put the absolute minimum in that you can get away with, and this through testing proved to be the absolute minimum.

It may be one of those things that Intronix says that they are not completely sure why it works, but it does.

The only ESD protection is the protection built into the Altera inputs, and that is also used for clipping when the input exceeds the Altera input voltage range.

Devices like this are handled with the same ESD care as the board under test, so they would never add protection to a 4.7pF capacitor. It would be 500V rating, and with a 150K resistor in parallel you would need over 3mA of ESD current just to reach that 500V. If you are exposing the analyzer to that much ESD energy, then forget it - find a new job.

Richard

[JoeyP]

When you see an input circuit like the one Intronix used for the voltage offset, you know that it was designed by by some poor engineer who spent a month or two juggling with board layouts, resistor values and resistor configurations until the best overall performance was achieved. It may be one of those things that Intronix says that they are not completely sure why it works, but it does.

I think you've left out one other possibility. Maybe they just know what they're doing   I've worked with analog engineers who could design such a circuit in minutes, and have the hardware optimized in an afternoon.

I too have a logicport which I've been using for years. I have to agree that it reliably does what they say, and is very friendly to use. I also have an older Agilent analyzer available, but I always find myself reaching for the logicport instead.

[amspire]

I have no doubt the Intronix designers know what they are doing, and were capable of circuit and track layout analysis, but we are talking about connecting transmission lines at 400MHz to different logic technologies that will have different impedances.

I suspect the only way to get the best compromise values for the damping resistors, track length and impedance and bypass capacitors is to do trial and error testing on a bench. For example, they may have deliberately designed for just enough overshoot at the Altera to boost the edge transition speed a little, but not too much to cause corruption of a high speed data stream due to unbalanced transmission line artifacts.  The parameters of the SMD parts at 400MHz all come into play.

Theoretical design is wonderful when all the parameters are precisely known. In the real world, most of the parameters are often not known.

Richard

[manu]

I use this logic analzer a lot and it saved me lots of time for debugging i2c or spi interface.
I really like the interpreters for the usual bus interfaces.
Its cost is quite low for such a tool. I recommand it!

[seattle]

I have no doubt the Intronix designers know what they are doing, and were capable of circuit and track layout analysis, but we are talking about connecting transmission lines at 400MHz to different logic technologies that will have different impedances.

I suspect the only way to get the best compromise values for the damping resistors, track length and impedance and bypass capacitors is to do trial and error testing on a bench. For example, they may have deliberately designed for just enough overshoot at the Altera to boost the edge transition speed a little, but not too much to cause corruption of a high speed data stream due to unbalanced transmission line artifacts.  The parameters of the SMD parts at 400MHz all come into play.

Theoretical design is wonderful when all the parameters are precisely known. In the real world, most of the parameters are often not known.

Richard

The thing with a logic analyzer, though, is you don't care about absolute delay. You only care about relative delay. And as long as all channels behave the same, you are fine. The fact is, lot of folks have this LA (myself included) and it works very well. Not one person has had an ESD issue, in spite of them not have any ESD protection.

I've debugged 125MHz SDRAM with it and it did fine. That is about the upper limit, as it's only 4 samples per transaction. But it's just barely enough to see what you need to see.

[regiscruzbr]

Resurrecting an old topic...

I wish they open source the software side so people could improve the functionalities . They will probably sell more hardware if they do so, don't need to release the firmware, only the communication protocol.

Several years that the software still in the same version without update.

It is a great piece of tool, only need a more powerful interface with more option of interpreters.

[Fraser]

I do not know the situation with the software source code but I have often come across the situation where the original coder has left the company and development of the software effectively ends.

With a Logic Analyser, it is often the software that makes or breaks the whole product. Releasing the source code into the public domain may not be in the companies interest as a result. The Logicport has a decent reputation but is now quite old. More modern LA's like the ZeroPlus Logicube offer masses of code interpreters. I bought a couple of those LA's for that functionality.

Fraser

[amspire]

Only just noticed this thread I started ages ago was resurrected in January.

I have been using my Logicport recently and it is annoying that there are no updates for 4 years, and no way to add new protocols.

Just looking at my photos and I noticed that the chip was an old Cyclone I chip. Could be an interesting project to use an input circuit like Logicport uses but use a recent Cyclone with a lot more memory.

Just musing on how to achieve the data compression.

Looks like they use a 33 or 34 bit clock storage and 34 I/O bits that they store in 36 bit x 2048  locations. The simplest way to store data at 200MHz or less would be that on an bit change, store the I/O bit state in one block of ram, and to store the clock counter at exactly the same time in another block of ram.

They probably have to store the incremental number of clock cycles since the last saved sample, rather then then an absolute clock. This has to be the way it works as a trigger can come at the end of a capture, and also you can capture for up to 10 hours at 200MHz sample rate, and an absolute 10 hour counter needs 40bits - more then the register can handle.

Logicport say they can store up to 2048 samples, but the method above can only save 1024 samples on the chip they use. I cannot really think how they do it. The maximum frequency with compression is 200MHz which is the maximum you can set a PLL clock to.

They have to be able to save a full sample every clock cycle if needed, so it is hard to do anything too complex.

Any ideas?

The 500MHz sampling would be done in a totally different way - that just stores one sample each 2ns  so they do not need to store any clock count.

Just thinking it would be pretty good having an open source Logicport-like analyser with a modern Cyclone chip.

Richard

[amspire]

Just did a 30 second capture with 16 channels with at least 12 channels regularly changing, and the sampling ceased after 1016 captured samples. Looks like they might be using the method I suggested above.

Another capture with the same 16 channels but only one bit changing did 1472 samples.

The trick they might use is that if the bit that changed on the previous sample has toggled this sample, just store the clock and just assume the same bit has changed again.

[manu]

Hi, this guy made this:https://blackmesalabs.wordpress.com/2016/10/24/sump2-96-msps-logic-analyzer-for-22/
with a Lattice dev board.
May be worth to see his hdl project.

[amspire]

Hi, this guy made this:https://blackmesalabs.wordpress.com/2016/10/24/sump2-96-msps-logic-analyzer-for-22/
with a Lattice dev board.
May be worth to see his hdl project.

Not bad. Needs a daughter board to provide the input protection and DC offect. I will have to take a look at that board.

I am getting the cheap Cyclone II development board, so I was going to experiment with that. Need some projects to teach myself FPGA programming. On thing I was thinking of is that if I attached a static RAM chip , I could be dumping samples to it, to make room for more in the limited high speed memory. Even when it is sampling at 200MHz, in practice it is only capturing a sample on a fraction of the clock cycles, so writing to the RAM at 20MHz would be fine. That way, I could increase the samples from 1000 to millions.

There are also Cyclone IV EP4CE6E22C8 boards available from A$23 delivered and they have over 3 times the internal memory of Logicport's Cyclone I chip.

[technogeeky]

Hi, this guy made this:https://blackmesalabs.wordpress.com/2016/10/24/sump2-96-msps-logic-analyzer-for-22/
with a Lattice dev board.
May be worth to see his hdl project.

Hardware aside, that software is pretty slick. It looks like he's using ASCII/ANSI block mode characters to draw the timing diagrams. Pretty cool and old school.

[robermeyer]

The guy that designed this was in his garage at the time.
He has sold tons of them.
He was working on an Analog version for a long time but obviously never shipped anything.
With the old Cyclone FPGA, it would seem obvious to upgrade the design to more modern and cheaper parts with lots more memory.
Then we would all buy another one!
I am disappointed he has not taken it farther.

[nctnico]

The guy that designed this was in his garage at the time.
He has sold tons of them.
He was working on an Analog version for a long time but obviously never shipped anything.
With the old Cyclone FPGA, it would seem obvious to upgrade the design to more modern and cheaper parts with lots more memory.
Then we would all buy another one!
I am disappointed he has not taken it farther.

With all the competition? The creator of the logic port has had a good run but nowadays it would be difficult to compete with what other USB based logic analysers out there.