That would be pin 23 on AGD422. I can confirm I also have connectivity from ASIC to OE# via 100R resistor. My continuity checker might have missed it in the first place, thanks for pointing it out. The flash chip connectivity is OK. I also probed DRAM chip. I figured that since there is activity on the flash, the boot process might have moved further. Pin 16 (/RAS) is held HIGH. According to the function table in the datasheet, that corresponds to DRAM being in Standby mode.
At this point, it can be assumed that the flash chip is corrupted and it is in a continuous read loop(maybe scope was shut off in the middle of a write process and got corrupted, who knows). There is not much, I can do at this point, but wait for the parts to arrive and build a simple JEDEC CFI logic analyzer to probe what happens in the data bus. that will probably take a few weeks. The U430A footprint will be my tapping point to the chip. To read the flash, I will probably have to remove R305 to suppress clock signals to ASIC and halt it so to avoid any digital interference.