Q1 is a N-type MOSFET. Q2, Q3, Q4 are NPN transistors. Google for the proper terminology for the three legs for a MOSFET (gate, drain, source) and NPN/PNP transistors (collecter, base, emitter), "output" is vague.
If Q2, Q3, Q4 are all turned on, by bringing their bases high enough, the gate of Q1 (same net as the collector of Q2) is pulled down to ground, Q1 is turned off, and ALL_SYS_PWRGD is open-circuit, presumably pulled high by a pull-up resistor not shown in the schematic.
If any of Q2, Q3, or Q4 are off, its gate of Q1 goes high (pulled up by R8156), Q1 is turned on and ALL_SYS_PWRGD is pulled to ground (0 V).
To answer your question, current flowing into the drain of Q1 flows out the source. Q2, Q3 or Q4 being off, combined with PP3V3_S5 being high, enables this current to flow.
Keep in mind that signals are sometimes active-low, i.e. a net labelled "S5" might be low if the S5 state is active, high otherwise. This is sometimes denoted by a line over the name, or a "#" or "!". This is certainly true of the PS_ON# signal of ATX PSUs, which you must pull down to ground if you want the PSU to turn on.