I have done some more research on the "RC Comp" and "Tap Delay" failures.
The 16754A service manual is a bit fuzzy on the details:
"
Comparators.The comparators are differential input/differential output devices that interpret incoming data and clock signals as either high or low. A threshold voltage provided by an internal digital-to-analog-converter (DAC) is coupled to the negative side of the differential signal through a precision resistor. Alternatively, this voltage can be provided to the data channels by a user supplied threshold line in the probe cables. There are separate internal DAC driven thresholds for the data and clock in each pod.
In order to achieve performance, an extensive calibration is performed on each comparator when the board is manufactured and the results of this calibration are stored as Calibration Constants in non-volatile memory on the logic analyzer board. These constants are loaded into the comparators at power on."
The 16760A service manual is phrasing this differently:
"
Comparators. The comparators are differential input/differential output devices
that interpret the incoming data and clock signals as either high or low. Threshold
voltage, programmed by the user through the user interface, is set by a digital-to analog
converter (DAC) coupled to the negative side of the differential signal
through a precision resistor. There are separate DAC-driven threshold voltages
for the data and for the clock. In addition, the comparator contains a diode in
which the junction temperature is monitored to ensure the module is being
properly cooled.
Much of the performance optimization for the module is accomplished by the
comparators, including channel delay setting (EyeFinder), programming of input
resistance, and frequency compensation adjustment.
Module operation such as
state clock modes and configuration are also done by the comparators. A digitalto-
analog convertor (DAC) provides the module threshold voltage for single ended
operation. The voltage at the DAC outputs are buffered to prove sufficient
line drive. An analog switch is used to channel either the module threshold
voltage from the DAC or the threshold voltage input from the system under test
to the comparators."
So, it looks like comparators themselves handle the adjustments to the "Input R", "OS Null", RC Comp" and "Tap Delay". Could it be that the comparators are "aging" and that it makes the SW unable to bring them back into spec via the available soft adjustments?
I played around with the 'vp' debug GUI (started via './vp -debug 255' from the shell) and I was able to "fudge" the various settings until the "RC Comp" and "Tap Delay" calibration passed. See attached p579.
I am, however, not certain that such a "fudged" calibration will actually work correctly. Perhaps this just makes the test pass but the H/W may still be out of spec. I know that the 16754A service manual talks about timing zoom performance validation via external pulse generator. I will study this topic some more.
I also will make an attempt to replace the FPGA on my burnt board (the one that was connected via 80- lead flat cables). I found what I believe is a direct replacement on Ebay. It is one speed grade faster but that should not matter as it is usually okay to go from a slower device to a faster, but not the other way around.
https://www.ebay.com/itm/145127678615If the FPGA swap works, then I will have to find a replacement comparator. I may take it from my other 16754A that has "bouncy waveforms" after FFFF to 0000 transitions as I'm at this point am not too hopeful of fixing that issue...
I will post a couple of IR images in the next post as the web site does not allow more images to be attached...
Thanks,
/John.