Build a reusable Z80 free run harness that wont damage the CPU or socket, based on a 40 pin turned pin socket. Crop and file smooth all the data bus pins. Take a 9 pin 8x 10K SIL resistor array and bend the pins enough to accommodate the remaining +5V pin (11) in the middle of the data pin stubs, bend its common pin up (away from the socket pins) and solder it to the sides of the stubs of the data pins with its body inside the socket footprint and not protruding below the plane of the pin bases, (some surgery to the plastic of the socket may be required). Jumper the common to the GND pin (29) on the opposite side of the socket using magnet or wirewrap wire. If necessary, protect the data pin stubs from shorting to the sides of a tall leaf spring socket by filing their outer corners for clearance and applying a strip of Kapton tape, notched to fit round pin 11.
It can also be worth building an adapter that breaks out the Z80 /WAIT signal with enough control lines to let you attach a single step / slow run circuit. (hint: if you even suspect the original circuit uses /WAIT, stack two turned pin sockets so you can intercept it from the main board and AND it with the /WAIT from your single step/ free run circuit. The basic single step/ slow run circuit is fairly simple: a 74xx74, a CMOS 555, two switches, a pot with a switch and a few passives. You can trigger it off a variety of Z80 control signals including /RD, /WR, /M1, /MREQ and /IORQ depending on the bus cycle you want to debug. I presented a similar circuit for the NSC800 CPU here:
Help! how to make a nsc800 computer? reply #263To make it Z80 compatible, delete the '138 decoder, taking /M1 direct from the Z80, and connect the circuit's /PS output to Z80 /WAIT.
N.B. some multi-byte Z80 instructions have more than one M1 cycle, so stepping may need multiple button pushes, however the address will increment on every push.
Its less useful on Z80 systems that use DRAM as holding the Z80 in a wait state disables DRAM refresh, but it can still be useful to check its actually executing from ROM, or if you trigger it off decoded /CS of particular memory or I/O chips, and add a status LED driven by U2B /Q, its useful to check the memory or I/O device is actually being accessed.