Repairing a current-to-voltage preamplifier

[magic]

If they allow you to power up the original module on a bench you could run some tests on it.

Check output voltage with shorted input to know the offset voltage, necessary for step two.
Check output voltage with open circuit input (and maybe some shield around it) to know the internal leakage current.
As above, but also measure noise.
Feed sinewaves through a 100MΩ resistor (say, 10x10MΩ chain for low cost and low capacitance) to see the input impedance vs frequency.

Any DIY build could also be tested that way. In real life, not in simulator.

[LoveLaika]

Thanks Magic. I'll try and see if we can run tests. It's always worth a try if I can.

I apologize for pivoting a bit, but I wanted to ask about one of the parameters. The manual stated that the -3 dB bandwidth specification at the fixed gain needs to be greater than or equal to 30 kHz. Now, I never took a course in op-amps, so the frequency stuff is a bit fuzzy to me, but I was wondering if my logic here is correct.

This is an IVC, but if you look at it a different way,  you could also see it as an inverting voltage gain op-amp. Looking at it like that, the ideal closed loop gain is 100 M / 100 k, or A = -10k. Converting that to decibels, -20 * log(10000) is -80. Using the parameters of the AD795 (one of the op-amps I'm considering using), the open loop gain is 108 dB, and it's GBW is 1.6 MHz. Following the chart on the AD795's datasheet, looking at figure 21, it's the open-loop gain, but the closed loop resistor feedback configuration reduces it down to 28 dB (108-80 = 28). Following along at 28 dB, it interesects the open loop gain line at around 50 kHz. That would mean that if the AD795 was used, the -3 dB bandwidth would be 50 kHz. Is this correct? After running some simulations in LTspice, I was designing my board and reviewing the specifications, and that got me to thinking about the bandwidth.


https://www.analog.com/media/en/technical-documentation/data-sheets/AD795.pdf

[magic]

No, to find the (approximate) -3dB point of closed loop voltage gain you find the point where open loop voltage gain equals closed loop gain, so 80dB. That's likely gonna be around 160Hz.

But what's the implication of that? It means that from that point, more voltage swing will be required at the TIP pin for the output to perform the same swing. If the TIP pin is being driven by a current source, the current source will keep cramming the same current into the pin and will increase TIP pin voltage as needed, until the output deflects enough for all the current to flow through the feedback resistor.

Therefore open loop gain determines input impedance of the TIA as seen by the current source, not its bandwidth. Bandwidth depends on feedback capacitance and the ability of the current source to force current into the rising input impedance of the TIA.

edit
Okay, it's not that simple. If OLG drops down to something like 10x, 100mV will appear on IN- for 1V on OUT and therefore only about 90% of the voltage across Rf will be visible on the output. So the conclusion is that we start to seriously lose I/V conversion gain as we approach the GBW of the opamp.

It would help you to simulate this circuit with ideal opamp, resistors etc. and inspect all the waveforms and see how they change with varying parameters.

[LoveLaika]

Thanks for the reply Magic. I managed to ask around, and I've managed to get data of a sample waveform used as a simulation. Approximating it to an ideal sinusoidal model, I'm also comparing it against a sinusoidal current source that appears to more or less match up with the sample data (-300 pA offset, amplitude of 30 pA, frequency of 10 Hz). It's just a little easier to look at for this simulation.

Working with that, now I see where I was messing up in my simulation. Comparing it with the ideal model, op-amp models that have around 5 pA or less (input bias current) seem to do very well. It's more important now to find an op-amp that works well in tiny currents rather than larger currents.

[aqibi2000]

If only a leg had snapped off and you haven’t confirmed it is faulty,

Just use a gold socket holder to give it some durability and strength and then you can fix the broken leg back on without worrying it will off break

[magic]

By the way, I tested parasitic capacitance between adjacent pins of DIP8 package, using fake chips from China which had some of their corner pins not connected to anything internally. Three different chips gave the same result.

From a corner pin to its neighbor it's about 0.5pF.

Might be slightly less between the central pins because they are shorter. No idea about SOIC pacakges - smaller pins, but maybe closer together.

[LoveLaika]

Thanks Magic. I was running my original circuit with my recently acquired data, and it turns out, like you said, a feedback capacitor wasn't really necessary. Based on the sample data it wasn't running nearly as fast as I thought it would be, so a feedback capacitor isn't necessarily needed. I continued to test my design amongst various amplifiers and diodes, and I've more or less narrowed it down to the following:

OP-AMP: AD795, LT1792, LT1793, AD549, and OPA140.
DIODES: CMOD6001, CMDD6001,  BAV116W, BAV199, 1N3595

Running these op-amps with my sample data with each of the various diodes and comparing it to the ideal op-amp model, the difference in output voltages range in the micro-volts. Given the parts limitations and restrictions, I think that's about as best as I can make it.

I was searching around when I found Dan Berard's homemade STM, and it got me thinking about how I need to readjust my board when dealing with pico-amps: using guard loops, voltage bias planes, teflon stand offs, etc. Figuring how to assemble the board appears to be a challenge in itself, moreso than finding components. That low-measurement handbook by Keithley suggested by KeepItSimpleStupid is proving to be useful.


https://dberard.com/home-built-stm/electronics/

[magic]

Check also the amplitude of tip input voltage - lower is obviously better. You have no idea what's the output impedance of the tip, huh?

Make a board for standard SO8 footprint, find a good resistor and play with some chips. Not sure what would be the advantage of 1792 over 1793, by the way.

Regarding input leakage, scroll back in the thread

[LoveLaika]

Thanks Magic. That leg lift trick seems great. I think I'm trying to do that, but it seems to work if the input pin is connected directly to the input and not connected to other components, like diodes and resistors.
If we had surface mount components soldered onto the board and used small wire to connect to the input in the air, would the SMD components still introduce leakage?

Apologies for asking so many questions, but if you don't mind a critique, what do you think of my board as a rough draft so far? Below is the top copper layer of my 4-layer board. All of the components (aside from the input/output posts) are surface mount, and there are no copper planes for the inner and bottom layers yet. I figured I could replicate the top layer onto all other layers to ensure that the same no-fill zones are in the same spots. I figured I would take a page from the ADA4530's book and use via fences and no-fill zones at the input signal. Focusing on the AD795 exclusively, the datasheet mentioned how I can connect the no-connect pins to the common node and form a guard loop that way. The issue is that the vias get in the way. How would you recommend I incorporate the guard loop and the via fence in my design?



https://www.analog.com/media/en/technical-documentation/user-guides/ADA4530-1R-EBZ_UG-865.pdf

[magic]

You know, I'm a lazy ass and crude hobbyist so I would lift the pin and wire in the air. Components can be "tombstoned" under the flying wire.

Can't tell you how much effort is required to keep 1pA or so leakage on standard FR4 board and how much is overkill, but a few harmless tweaks come to mind:

Did they tell you to put the vias that close? I would put them farther, under the ground pour. The more resistance between IN- and any kind of ground the better, I think. The point of guarding is to bias the other end of the "resistor" made of PCB material to something approximately equal the signal voltage, but not to reduce PCB resistance.
Is 4 layers actually of much benefit for leakage over 2 layers? (No idea).
Run a guard under the IC, route the output on the right side. One VCC capacitor will need to move.
Make space for a few resistors in series, unless you are sure you will find a resistor with suitably low capacitance. You can always solder-bridge unnecessary footprints, it's not a mass production item, meh.

[LoveLaika]

Well, that does certainly feel like the best option at the moment.

I was trying to replicate what AD did in their evaluation board, or at the very least try to incorporate some of their techniques into my design. I was just placing the vias along the guard ring to act as a via fence along with the guard ring itself. Once I get the initial guard ring design down, I'll place more vias around whatever free space I can around the board to connect the ground pours.

While I understand the idea of adding pads for more resistors to reduce the capacitance, there would be exposed copper pads if left unpopulated. Wouldn't that cause more of an issue by acting as an opening for noise to jump in?

[magic]

Populate the footprints starting from the input side. Leave any unused and shorted footprints on the output side, where driving impedance is low.
Also, a resistor footprint with a solder blob on it is not even that much larger than a straight PCB trace it replaces.