Repair of Solartron 7081 SN#718

[Kosmic]

So it look like the noise align perfectly with the Glug drive.

The big spike is the + Glug drive and the small one just after the - Glug drive (see picture). +Glug and -Glug comming in the Integrator look fine thought. So i'm still not sure if it's really a problem or not.


I found that adjusting the main clock has a huge impact on the measurement  noise (not vref noise).

[pigrew]

GLUG+ and GLUG- are never on simultaneously. There's a nice 20us delay between them. The spikes are happening as GLUG+ or GLUG- is turning ON. Perhaps TR203 & TR204 (3N163 4-terminal p-channel e-mode MOSFET) are turning off too slowly. These ground "GLUGS" between pulses.  They have a threshold of between -2 and -5 V (relative to 0V).

TR202 (VN67AK) has thresholds between 0.8 and 2 V (relative to -10 V). So, as -GLUG turns on, there is a time period when both the -10 reference and GND are connected to GLUGS (causing the shoot-through).

I can't help but think that these pulses are damaging the Zener reference. I'll have to study the FET Drive circuit for a while longer. It seems to me that the turn-on-edge is too slow. My oscilloscope shows about 25ns edge time, but I'm not using optimal probing techniques.

EDIT: One "fix" would be to tear out the entire circuit, and replace it with a CMOS analog switch IC, like the ADG1404. I can't think of a less invasive solution at the moment.

On the attached image:

1) -GLUG
2) GLUGS
3) +GLUG
4) -10Vref

I found that adjusting the main clock has a huge impact on noise thought.

You mean tuning the oscillator's capacitor to make the control voltage around 2.5V? Or injecting a lower-noise clock?

[Kleinstein]

I think using a CMOS switch chip instead of the discrete MOSFET circuit is an option. However the ADG1404 might need a level shifter as the control signal is -15 V to -10 V. Especially for a first test a higher on resistance switch might be OK.

A current through the FETs to ground sounds plausible - more like a design weakness than a broken part. A faster control signal could help, but it would not totally eliminate the problem.

[Kosmic]

You mean tuning the oscillator's capacitor to make the control voltage around 2.5V? Or injecting a lower-noise clock?

Yes, just tuning the oscillator's capacitor. But the oscillator is really not stable. I saw in the manual that there is a option to replace the oscillator with a crystal clock. Not sure if the 7081 has the same option. I might try that later on.

[pigrew]

I think using a CMOS switch chip instead of the discrete MOSFET circuit is an option. However the ADG1404 might need a level shifter as the control signal is -15 V to -10 V. Especially for a first test a higher on resistance switch might be OK.

A current through the FETs to ground sounds plausible - more like a design weakness than a broken part. A faster control signal could help, but it would not totally eliminate the problem.

I spent some time trying to design a discrete logic level shifter, but never got anything I was happy with. I believe a good solution would be to buy a logic isolator IC (SI8423BB), and use it to shift up the voltages. There are some other switches that look acceptable and do not require logic level conversion (ADG5409), but they have a worse delay time and higher resistance.

I had been worried that the switch transition time (i.e. propagation delay) is 150ns (nearly a clock cycle), and is strongly temperature dependent, but the delay in the rise and fall are equal, so will cancel each other out. Also I feel better because the Solartron driver circuit has unequal propagation times for rising edge of glug and falling edge of glug, there should be some built-in calibration to fix mismatch.

The mod will cause larger thermal voltages to form, but I hope that it won't hurt the accuracy too much.

What's the proper way to test the modification? I'm planning to go ahead with this mod, but have not convinced myself if it will improve the meter's performance.

Is measuring the "test0" noise good enough? I don't have the equipment and patience to perform temperature coefficient measurements. I may do some linearity testing versus a 34401A.

[Kleinstein]

The ADG1404 CMOS switch also has some down sides: it has quite some parasitic capacitance (higher than the FETs it is replacing). So there would be not cross conduction, but the charging / discharging of switch capacitance - so the effect might be similar. With the ADG1404 it is a 10 V step at some 90 pF or about 40 pF more than with the original FETs - so some 400 pC. With the cross conduction it is some 25 ns with a resistance in the 500 Ohms range (the P-FETs are 250 Ohms and thus rather high resistance). Thus up to 20 mA for 25 ns which is 500 pC - however the cross conduction might be less than the full slope time.
So making sure the switching is fast might be more effective than the CMOS switch.

Some of the current might be normal just because of the capacitance - so some of the spikes might also be normal for the design, though not really desirable. Making the reference part lower impedance might be still an option.


A higher resistance of the CMOS switch would cause some extra gain drift - though not that much. The maybe 1.5 Ohms of the switch will have a TC around 6000 ppm/K, but relative to 100 K this is only 0.1 ppm/K.

[pigrew]

It's been a few days more, and I'm starting to realize that I'm actually chasing a few different improvements.

The first is reference stability. Do the spikes reduce the long term stability of the Zener reference? Maybe. Without a large sample size, the answer is unknowable. However, the spikes can't be good. As Kleinstein has mentioned, the 0V reference is through ~500 ohm resistance of the PFETs, so it isn't too bad.

The second issue is temperature stability. The VN67AK's have ~5 ohm Ron when Vgs=5. Assuming the previously mentioned TC, this may be about 0.4 ppm/K. The ADG1404 has a smaller Ron, so is likely a good change.

I expect noise to be largely unaffected by changing the switches. Using an external clock may be helpful here.

Now, I think the big thing is INL in the very upper part of the range. This depends on how constant the glugs voltage is. The question is: Does the glugs voltage stabalize within the minimum glug width. Using a 10Mohm probe, it looks like it takes 350us to read the reference voltage, and starts about 30 mV off. I used the zoom mode of the scope, so the input amplifier was not saturated. Using the completely wrong FET model (I can't find VN67 spice models, I'm using 2N6660 instead), I see 0.5 mV deviation within the first 40 us or so. I think that something is wrong with my measurement (bad probe HF compensation?). I guess I'll need to compare the 7081's INL with a 3458A to see how good it is without the mod, and then finally with the mod.

I'm not so worried about the capacitace as I am about the switching time. I'll do some bench tests with a 100k load to see how fast switching is with the proper load condition (using an active probe).

Oh, and I finally put together a shorting plug with the LEMO-style connector. High->Low->Guard->Low_source->High_source. I built it with 67/37 solder and copper wire from a UTP Ethernet cable. I didn't cut the copper, I folded it and pushed it into the sockets before soldering.

[Kleinstein]

For the TC due to the Ron of the FETs, one has to take into account that there are also MOSFETs at the signal input. So there will be some compensation and a lower Ron at the reference switches may not be good. I have not checked the Ron values there.

I agree that very short GLUG pulses might be a problem with the way the gate drivers are build. At least this might be a point to check - though much of this would be at the very upper end of the range (e.g. >11 V in the 10 V range). I don't think the small slow settling of the gate voltage would be such a big problem the R_on is not that different from 10  V to 10.03 V.

The spikes are really large, but I still would not expect damage to the zeners. The current does no go that much higher than normal and it is too fast to cause thermal effects. The trouble I see is that the length of the spikes might change with transistor / OP temperature and this way add to the TC. If the spikes change with input voltage this might cause some INL.  After looking at the switches I am no more surprised to see significant spikes, though it is still way more than I have expected. Maybe 500 mV of load transients are kind of normal for a reasonable voltage regulator and a similar stability should be possible with the reference buffer.

The bigger excursion is to the positive side, so from something like having too little load to the reference buffer - this would not be directly from the extra current through the P-channel fets, but more like the gate drive current or maybe some overshoot after a negative spike. Is it possible to resolve the wave-from of the spikes to seen if they go up or down first.

[pigrew]

Is it possible to resolve the wave-from of the spikes to seen if they go up or down first.

I just did a few more oscilloscope captures (sorry I'm using my cell phone camera... it's much faster/easier than floppy disks or GPIB).

I captured traces using a P6205 active probe.

First is the positive reference. There are two different waveforms. One immediately goes up, the other goes down and then up.

The negative reference voltage goes up first.

The next captures are of the "glugs" net. When the +plug is enabled, the spike is evident, and reaches about 1.5 V above Vref. It settles fairly well after ~300ns.

When -glug is enabled, there is a bit of an upwards spike from GND, I guess due to charge injection. It then spikes down to -11.52 V. It may take about 300ns to settle, also. When -glug is disabled, It again bounces down to -11.6 V, and slowly drifts back to GND over ~400ns.

In 3 nines mode, the glugs are shorter. The min positive time is 80.8us @14.2V. The min negative time is 81.8us @-14.2V.  The period is 1.56ms.

In 4 nines (and above), Min positive glug time is 395us, min negative glug time is 394us. The period is 6.22ms.

I'll think about this later, and do some math to get an idea about how these numbers will effect the linearity. For 3 nines mode, the glug duration is definitely short enough to run into INL issues, but due to the reduced accuracy spec, it's likely in spec. For <=4 digits, 395us probably will cause a small amount of INL, based on the oscilloscope captures of the glug waveforms.

[Kleinstein]

The spike for the positive reference going up directly suggests this might be from the gate capacitance - so the positive slope of the gate drive pushes the voltage higher than it is supposed to be. With a rather limited sinking capability (just the resistive dividers) there is not much stopping it from going rather high. A very simple way to get a little improvement might be adding some more load to the reference (e.g. an resistor). One problem here is that making the reference source stiffer might increase spikes on the ground networks or coupling from +ref to -ref.


I don't see a INL problem for the 3 or 4 nines modes. The min on times are still relatively long compared to the settling time. So the reference will be well settled before the next switching comes. Just having the slow switching with some overshoot / ringing is in a first approximation only adding some offset. It would be only if the wave-form changes or two switching spikes interact that it causes INL errors.  One possible effect on switching slope might be from the C210*r210 = 2.2 nF*10K = 22 µs  time constant in the gate drive circuit. But it is still way shorter than the 80 µs min on time.

[Mickle T.]

I don't fully understand, is there are INL problem with this DMM? All 7081 I seen, has a nearly perfect INL in range of 0.1-0.2 ppm /+-10V.

[pigrew]

I don't fully understand, is there are INL problem with this DMM? All 7081 I seen, has a nearly perfect INL in range of 0.1-0.2 ppm /+-10V.

No INL issues discovered. I am investigating spikes on the reference voltage, and guessing that there could be INL issues when overranged (close to 14 V).

In 3 nines mode, the result is constant (pretty much no noise on the result). The INL is better than the resolution of the result, so all is well.

In a very rough measurement, I didn't see any issues >3 nines (within ~20 ppm INL, for my very rough masurement).

I'll now plan to keep the current circuit (risk is more than possible gain), but see if increasing the load to the references helps with the switching noise. As I have the ADG1401 in hand, I'll make some out of circuit measurements of its switching speed.

On a proto-board, the ADG1401's delay is about 150ns. I notice a bit of charge injection along with some ground bouncing (likely caused by not so careful wiring). There is about 0.7 V ringing on the output, perhaps adding a bit of capacitance on the output would improve that (the load is a few pF with 100kohm).

[czgut]

Re input cable:
I would rather avoid using close Hi with Lo:
1. isulation issues: if Your cable has poor iinsulation, You will get leakage between them. It may be meaningfull at 10^4 kOhm measurements.
Iven at 1MOhm level, original Solartron cable lowers reading 0.5   ..1 ppm due to leakage.  Pure cable may  lower readings 5ppm or more..
2. Solartron 7081 is somewhat sensitive to  noise ( noise changes reading  by temporary saturating amplifiers). Therefore good screen around test leads is important whem You will measure Vdc on Low levels, as well as when measuring AC voltages.

Metal plug and  socket will equalize temperatures (to lower thermal EMF) of external/internal cables/connections.

Most od current will be carried by blue (Low I)  and yellow cabel (Hi I  in Ohms Mode)   (1mA @ 0.1 ...10kOhms range)
Input bias Hi current  should be below 50pA, Lo +Guard should be below 120pA.
I would choose good quality, flexible, well screened test cable. (I would not save on cable).
Low thermal EMF Plugs / forks are very important at Low Vdc measurements. I would look for gold plated copper beryllium or something similar. 
Good luck!

[czgut]

Re: PLL to follow line frequency. The circuit used at 7081 has very narrow voltage gap where it works OK. So it is difficult to set it correctly.
But it is worth of doing it, if You need low uncertainty at low voltage   levels (1V, 0.1V).
Without exact tracking of line frequency and integrating Ux exactly N  periods of line voltage, it is very difficult to dump net noise to uV level (influence of AC on DC reading)..

[borghese]

PLL to follow line frequency. The circuit used at 7081 has very narrow voltage gap where it works OK. So it is difficult to set it correctly.
But it is worth of doing it, if You need low uncertainty at low voltage   levels (1V, 0.1V).

Can you explain your method to adjust the PLL or is it the same as described in the manual?

[Mickle T.]

Re input cable:
I would rather avoid using close Hi with Lo:
1. isulation issues: if Your cable has poor iinsulation, You will get leakage between them. It may be meaningfull at 10^4 kOhm measurements.
Iven at 1MOhm level, original Solartron cable lowers reading 0.5   ..1 ppm due to leakage.  Pure cable may  lower readings 5ppm or more..

I think you uses a dirty/failed cable I had a several 7081's and full sets of optional leads for it, including low thermal ones. All leads are well screened, have a PTFE insulation and gives the same measurement results in 1MOhm range. No 0.5...1 ppm due to leakage.

2. Solartron 7081 is somewhat sensitive to  noise ( noise changes reading  by temporary saturating amplifiers). Therefore good screen around test leads is important whem You will measure Vdc on Low levels, as well as when measuring AC voltages.

The 7081 noise sensitivity has nothing to do with the input amplifier saturation. On the old revision of DMM (PCB5 rev. E and earlier) the floating RATIO inputs has a poor FET control levels (TR505, 506, 508, 509 switches), so a fast transient/noise, picked by RATIO inputs, could get to the ADC input. The second problem with old 7081 was a poor GUARD routing, which was corrected in a new DMM revisions.

Without exact tracking of line frequency and integrating Ux exactly N  periods of line voltage, it is very difficult to dump net noise to uV level (influence of AC on DC reading)..

Phase locking to the mains raises more issues than it resolves. Are you uses an ancient auxiliary diesel-generator for DMM powering? A 51.2s integration time and a narrow limits of frequency deviation, specified for the national grid, gives an excellent NMRR in theory and in practice.

[tggzzz]

Phase locking to the mains raises more issues than it resolves. Are you uses an ancient auxiliary diesel-generator for DMM powering? A 51.2s integration time and a narrow limits of frequency deviation, specified for the national grid, gives an excellent NMRR in theory and in practice.

It isn't the same point, but what is the effect of failing to lock to the mains frequency?

I ask because when I first received my 7081 it was noticeably noisy. After tweaking the PLL as per the manual, it became significantly less noisy.

Sorry, I don't have comparative figures, because at that stage I was completely ignorant of the entire topic and was just wildly flailing around.

[Kleinstein]

Not locking to the mains frequency can cause a small very low frequency contribution to be added. The line frequency suppression is rather good due to the long integration time, but not perfect, especially if the line frequency is a little off. Due to the long time even a 0.01 Hz off can be relevant - essentially no more specific suppression for 50 seconds integration.

When locked to mains frequency the suppression would be better (as the frequency is correct) and the additional small signal would be more constant.

The non tweaked PLL could be in a state of not always locked and thus have considerable phase noise. A non locked PLL is usually worse than a locked PLL or a fixed frequency. Also the frequency can be off quite a bit when not locked.

How good the PLL lock will be also depends on the line waveform. The implementation in the Solartron is also not very good, as it only used 10 Hz phase comparison and thus 1/5 or 1/6 of the possible frequency. An analog PLL with a very low frequency loop filter is tricky anyway and can be sensitive to mains hum or similar effects.

So ideally one would have the choice between a fixed frequency and a better PLL. It depends on the signal which one works better.

[pigrew]

As I mentioned a while ago, my unit has significant phase noise on its clock. My current guess is that it is due to the modern use of switching power supplies, causing innumerable spikes which confuse the power line detector circuit, causing the PLL to never really lock. I had initially thought it was due to the optoisolators, but notching changed after replacing them.

I want a way of measuring the effect of the mains/PLL, before trying to tweak things.

What's the best way to measure the goodness of the clock/PLL? Look at the voltage noise of a shorted input (or test0)? Or wind the input cable around a power line a few times to actually inject the mains into the DMM and check that the input is still zero? Because the frequency seems to change on the order of every minute, I think I need to focus on the results of the 8.5 digit mode.

[tggzzz]

I want a way of measuring the effect of the mains/PLL, before trying to tweak things.

I omitted to do that, partly because I didn't have any good way of measuring it.

What's the best way to measure the goodness of the clock/PLL? Look at the voltage noise of a shorted input (or test0)? Or wind the input cable around a power line a few times to actually inject the mains into the DMM and check that the input is still zero? Because the frequency seems to change on the order of every minute, I think I need to focus on the results of the 8.5 digit mode.

Have you considered logging the ratio of the 5.xMHz and 50Hz frequencies with various averaging times? Ideally it should be a constant, but...

[Kleinstein]

For the mains PLL, the first point would be to check if the 50 Hz signal behind the OK is good (low jitter 50 Hz). With poor mains quality it might help to have some low pass filtering at the 50 Hz level (e.g. before the OK).

It might be also worth looking at TP607, the output of the PLL. However this point is sensitive and high impedance and thus testing can disturb the PLL. The shorter and more regular the peaks, the better is the PLL lock. Pin 1 of the 4046 could be an alternative test-point that is not that sensitive and would give pulse of just one polarity.

To see the effect of the frequency there would be two points to test. Once with a stable signal, like the internal zero - this would be slightly sensitive to clock jitter / modulation. The other test would be with an intentional 50 Hz (mains) signal (e.g. 2 V in 10 V range form a small transformer) to see the effect of a wrong frequency on the 50 Hz suppression. It might also work with a 50.0x Hz signal from a separate generator. Probably no need to use the super slow 8 digit mode. The 7 digit mode should be more suitable as one gets more points.

[pigrew]

I made a nice plot showing the correlation of my PLL's instability with the measured voltage. I noticed a strong trend using test0 with 7 nines. I did an 8-element moving average in Excel to process the data. The control voltage (C806neg to TP904) was read by a 34401A in high-impedance mode. This was somewhere around 0.8 ppm pk-pk of the range.

[pigrew]

Probing the demodulator drive (PL501/30, should be the output of the AC zero-crossing detector), shows oscillations in the power line frequency (from 59.97 to 60.02 Hz, or so), so my situation is that the mains here is awful, and/or the PLL filter is too fast.

And to support the view that my mains is awful, I probed the AC line with my frequency counter (using a ProbeMaster 4231 differential probe), and I'm seeing the same sorts of frequency oscillations, so the zero-crossing detector seems OK. There is a wind farm 20 km North of here. I don't know if it could be causing issues.

Injecting a low-phase noise clock seems to be the answer in my neck of the woods. Using a slow enough loop filter would make startup quite slow and annoying.

[Kleinstein]

The mains frequency should not depend on the local generation. The frequency is essentially the same for the whole grid, so likely the US and Canada.
The frequency counter might have the same problem getting a stable trigger from a not so perfect 60 Hz signal. The usual counters are not really good in measuring the mains frequency, as they have problems to get an accurate trigger. Some oscillation of the power line frequency are normal. For some reason I can only find Web pages to show the current European grid frequency, e.g. http://www.mainsfrequency.com/

The PLL filter tends to be rather fast, but this is more like a limitation of the analog implementation. To ensure locking even with drifting VCO the filter also can not be very slow.  The solution could be a digital controlled PLL to allow a fast startup with a long time constant. Some analog tricks are possible too - like a separate mode to get the initial lock.

A stable, but constant frequency is likely the easiest solution. Unless you measure a signal with lots of AC superimposed this should not be a big problem.

[tggzzz]

For some reason I can only find Web pages to show the current European grid frequency, e.g. http://www.mainsfrequency.com/

UK: http://www.gridwatch.templar.co.uk/ and you can download datasets going back to 2009.