It's a design quirk of the Jameco clock- to run PMOS into a CD4049UB buffer. With the old PMOS slow edges and mushy logic levels, the CD4049 doesn't clean that up much at all and you get digit driver overlap.
With no pulldown it takes forever 400usec to go below 2V.
I thought the digit ghosting could be fixed adding by adding six 47k pulldown resistors (pins 3,5,7,9,11,14 to GND). That did clean up the logic 0 level but still a tiny bit of ghosting.
Adding the pulldown somehow weakens the output drive so it seems to make things slower (if you go lower value, to say 10k).
The MM5314 datasheet is depletion-mode PMOS, +VSS and VDD=0V so I read that wrong - so sink is source and source is sink for output current specs with my NMOS convention I'm used to... I see about 2mA source and 0.5mA sink. With the datecode 1972 IC, about 2usec digit overlap depending on temperature, digits displayed etc.
If there was a 4049 compatible IC powered at 15V with better gain, that could fix it too.