You can't complain about 3.2 V offset on a 500V/div range! Even if it uses a 10 bit ADC, that is one ADC count, remember that full scale is +/- 2000 volt! In other words, there is no offset, you are imagining a problem, at least for that one range. Does the SPC procedure reduce the offset in all other ranges to less than 1/10 of a division? (e.g. 5 V/div range, offset should be < +/-0.5 V). If so, then you are doing fine.