Roland D50 CPU INT for slave IC stuck on low. RD & WD not pulsing

[gkmaia]

My main issues here are:

Why my Synth IC is sending a low signal to the CPU IC INT0 input?

Why my CPU WR & RD are stuck on high instead of pulsing?

Is it more likely I have a faulty CPU, Synth IC something else?

Charts bellow show probing on key points of CPU and Synth comparing a working and a faulty PCB

[LateLesley]

I looked up the service manual, which shows the chip pinouts. Pin one of the chorus chip (the M887136) is th reset pin, and your chart shows it being held low. That's coming from the gate array IC 28. I would check it's reset pin (24) and if it's low, trace back from there. It looks like everything is being held in reset.

http://www.synfo.nl/servicemanuals/Roland/D-50_SERVICE_NOTES.pdf

[gkmaia]

I looked up the service manual, which shows the chip pinouts. Pin one of the chorus chip (the M887136) is th reset pin, and your chart shows it being held low. That's coming from the gate array IC 28. I would check it's reset pin (24) and if it's low, trace back from there. It looks like everything is being held in reset.

http://www.synfo.nl/servicemanuals/Roland/D-50_SERVICE_NOTES.pdf

Thanks for the feedback.

The pin1 my chart shows being low is the INT. It outputs from Synth pin 1 and inputs on the CPU pin 18.

The pin 1 you refer on the Chorus is connected to chorus VDD. So as long as the chorus is getting 5v the RES pint will be high, which is.

As per by all being held on reset good idea. Did check the other ICs with reset instruction and they all seem fine. I updated my chart with this extra data.

[JFJ]

Why my CPU WR & RD are stuck on high instead of pulsing?

The WR and RD lines are set high when the processor doesn't need to access any external addresses (e.g. while executing the code held in its internal ROM and only writing to the internal RAM or registers).

The WR and RD lines also remain high when the processor is in HALT or STOP mode. Those modes are entered by setting the appropriate bits in the Standby Control Register. Normal operation is resumed when the processor receives a pulse to its RESET line, or when a valid edge is input to the NMI or to an unmasked interrupt request line. When in HALT or STOP mode, the processor internally shorts its X1 pin to VSS (to prevent clock generator leakage current). So, if X1 is grounded, then that would suggest that the processor is in one of its standby modes STOP mode.

(Edited to correct HALT mode mistake).

[gkmaia]

Why my CPU WR & RD are stuck on high instead of pulsing?

The WR and RD lines are set high when the processor doesn't need to access any external addresses (e.g. while executing the code held in its internal ROM and only writing to the internal RAM or registers).

The WR and RD lines also remain high when the processor is in HALT or STOP mode. Those modes are entered by setting the appropriate bits in the Standby Control Register. Normal operation is resumed when the processor receives a pulse to its RESET line, or when a valid edge is input to the NMI or to an unmasked interrupt request line. When in HALT or STOP mode, the processor internally shorts its X1 pin to VSS (to prevent clock generator leakage current). So, if X1 is grounded, then that would suggest that the processor is in one of its standby modes.

Hi JFJ. Such great comment, thanks for that.

I have two boards. One that works and one that does not. I removed all ICs (gate arrays, ASICS, ROM & Ram) from both boards to see if there was an IC that when removed or failed would stop the CPU from pulsing RD WR.

The working PCB after all the butchering still pulses RD WR. The faulty one still do not and as you wisely said it shorted the X1 to ground permanently. Even when the DUT is off it is still shorted.

The RESET is connected to main supply so it is 5v as soon as the device is on. So brought it to low to see if that would reset. But still not pulsing.

Last thing was the NMI. By default it should be getting a 5v from the rail as soon as the device is on. And so it does.

When comparing both boards down to bare CPUs they are pretty much the same apart from the CPU. One still pulses and the other do not.

I have a few questions based on the datasheet.

"When in HALT the CPU stops and clock continues to run and maskable interrupts (P21-P23/Inte0-1Inte2) can restart the CPU".
Maybe bring a HIGH all INTs by connecting them to the 5v rail directly?

"When in stop mode, the CPU and click are both stopped A RESET pulse or the nonmaskable interrupt (P20/NMI) is required to restart them. "

What I did was:

• Removed the RESET from 5v rail
• turn the DUT on
• turn the DUT off
• Connected RESET back to 5v rail
• turn the DUT on
• turn it off

Should I have done?:

• turn the DUT on with RESET connected to 5v rail
• Isolated the RESET from 5v rail to simulate a LOW pulse
• Connected RESET back to 5v rail

[JFJ]

When in HALT or STOP mode, the processor internally shorts its X1 pin to VSS...

The clock is only stopped in STOP mode, as your attachment shows. Sorry for my mistake (now corrected). It's been a long time since I worked with the uPD78312, and my memory is clearly not as good as I thought it was.

"When in stop mode, the CPU and click are both stopped A RESET pulse or the nonmaskable interrupt (P20/NMI) is required to restart them. "

If the uPD78312 is in STOP mode from the onset of power-up, then I doubt that a RESET pulse or an interrupt signal will wake it up. The device may simply be faulty. A fault could be electrical or due to a firmware problem.

The likelihood of a firmware problem would be greater if your processor is marked uPD78P312. That type of processor has an internal electrically programmable PROM (one-time programmable if there's no window), instead of a mask ROM. The PROM stores data as a charge on the floating gate of its FET storage elements. Over time, some gate charge can leak away - causing programmed 0's to revert to 1's. Thereby, corrupting the processor's firmware.

[gkmaia]

Yes, there could be an eprom. I did find a bunch of literature about these microcontrolers. But I think over the time NEC messed around with these labels.

My hint is that my version the 78312G has just a masking ROM. I managed to order a couple NOS masking ROM 78312A(A).

As the FIRMWARE sits on another EPROM IC I hope what comes on the masking ROM is just standard code. If not, then well not much I can do.

But interestingly I places the non pulsing CUP on my good board. It did not pulse first time. Started the board again, it pulsed. Also cannot blame the EPROMs as it pulsed with both.

I need to do more tests between the boards but seems the processor is not faulty. Not so sure it, but seems to be good.

[gkmaia]

Have a look at the spreadsheet attached. Probe your signals and compare to mine.

Early to say you got a faulty array. You likely got a faulty IC somewhere.

[Yekuku]

Hi guys, I am responsible  for bringing up this old thread.
I am experiencing exactly the same issue with  gkmaia , I have a dead D-50 that has CPU INT0 pin stuck on low and RD & WD not pulsing.
According to this very useful thread, my limited  understanding is that the CPU is in HALT mode because it is waiting for for the SYNTHE IC to respond to INT0.  X1 pin is not grounded , so I believe that the CPU is ok (not in STOP mode).
Any ideas of what could be causing this ? I hope not the synthe IC!
I havent done any troubleshooting on the synth IC.
thanks !

P.S. gkmaia thanks for spreadsheet !

[gkmaia]

Cool, let us know how your findings lineup with my working D50 spreadsheet

[Yekuku]

I cant measure the 32mhz crystal,  I have replaced it, but it didnot  make any difference. The unit is still dead , voltages are ok, no shorts on board, LCD shows  rectangles.
My oscilloscope goes up to 1Mhz, I am using a logic probe to take readings.
Here are my results compared to the working board  and a thermal picture of the pcb, the chorus IC seems not so active.

[Yekuku]

I am afraid that it is either the Synthe IC or the Chorus IC, both are custom ICs
I have basic understanding of digital circuits,  I am no EE by any means, so please feel free to correct me, if my assumptions are wrong.
Trying to figure out the boot sequence , this helps a lot :

The D50 EPROM throws a start up routine where the CPU checks if the Gate array, Synth & dyna board INTs are present. Then the Gate array also checks if reverb and chorus are present. If they are all present the CPU boots up.

The problem I am experiencing is probably  CPU HALT due to SYNTHE IC not responding to INT0.

What could be causing this to Synthe IC?
By checking the signal flow the reverb IC sends Ready signals (pin 6-10) to a dual 2 to 4 line decoder (IC17) which activates OE on synthe IC and chorus IC.
By comparing readings on the working and non working board, I am getting pulse on  Synthe IC’s OE pin but chorus ICs OE pin is held High.
This could be a problem with the decoder IC17 or the reverb ic not sending proper ready signal.
My hopes are on the IC 17 , it is a 74HC139, the problem is I don’t have any and due to  the isolation i can’t get any. I have a  74LS139, will it work ?

[gkmaia]

Yes, sound like you got a faulty ASIC. I would agree with your logic.

Give it a go and replace the 139. I cant see it causing any harm.

When I fixed my one I com across lots of people with faulty Reverb and Chorus ASICs.

I will try to find sometime later this week to get these interrupts on a logic analyser so we can check what the program asks the CPU to do in terms of boot signals from these ASICs.

[Yekuku]

Thank you so much for the support Gkmaia, without your findings I would be lost.
The 74ls139 that i have is in DIP package,  not impossible but it will be quite hard to install.
I am searching a pile of junk pcbs  that i have, but i have not find any smd  139 yet.
Anyways ,
I will keep you updated  , many thanks

[matrix12x]

@Yekuku were you able to get this to work? (replacing IC17) or was it the reverb chip?


I seem to have a similar issue and just ordered a 74HC139.

[matrix12x]

Just to update for people reading this in the future. In the end I had to swap out my CPU and my Synth IC and then it worked.