ADVANTEST R9211B

[m k]

Don't worry about multiple replies.
I'm just sitting here feet up and watching pictures, and poking the keyboard when something comes up.

5F1Cxx ?
5F08xx *CSRTC
5F34xx ?

It seems that I've all the time seen that CRT controller is somewhere in the I/O map as a CRTC, somehow I've mixed it with Real Time Controller.
So actually 8245B is a CRT controller, but the old one, so it is no more and current one can be very different, or it obviously is very different, but how different its I/O map is, we don't know.
So address 5F34xx can be very legit.

82C79 KBC, RTC, X2864 E2PROM and program module, those are clearly a group.
I/O map indicates that one D71054 timer is also part of it.

*BZON is easily a buzzer and can be controlled by 1/3 timer of the chip near by.

*INTCLR is tricky, or maybe not, maybe it's for the connector near by, INTensity ControLleR perhaps.

Counter chip is bidirectional, so max 4 addresses can be for 1 counter chip.
If that style is used then connections can be coded through something instead of its A0 and A1 directly to CPU address lines.

Upper edge of ROM module has some logic chips.
xx00 is 4x 2 input NAND
xx240 is 8 bit buffer/driver, same as xx244.
xx138 is 3to8 line decoder.
xx02 is 4x 2 input NOR
xx139 is 2x 2to4 line decoder.
The module has also 3x 32 pin connector and all of those logic chips are not needed for memory access.
So memory part is different, but DIP switches can be a part of the group.

xx240 is also very suitable for those DIP switches, resistor network also.
On the other hand many traces go directly past that chip, maybe it's just an angle of a picture.
2nd part is clearly for DIP switched, 1st one not so sure.

Top right of the ROM module picture is connector J2.
It's clearly connecting something near those DIP switches up or down.

If those DIP switches are a MODESET there must be a 5F18xx coded to that xx240.
Whole address contains 16 bits, that's too much, but last 8 or 9 is easy.
Since I/O map is divided as it is, it's more likely only 8 bits.

---- ---- 0001 1000 xxxx xxxx
Variations are many, either gates first or decoders first.
If both xx240 parts are uses 2x 2to4 line is spot on, that's also spot on for ROM chips.
If decoders are last then final address polarity doesn't matter.
xx02 pins 8 and 11 are shorted, it's clearly narrowing something.

If address coding is more predefined, like is rational if motherboard parts are included, the rest may be as narrow as 2 or 3 bits.
Then single decoder chip would be enough.

If MODESET is 8 bits wide with only 1 address, xx240 enable pins 1 and 19 are connected.
Output is 3-state, so no other latches are needed.
More than 1 MODESET address would be better, then sanity check is also possible with unused data bits.
And if that is the case then also 5F1Cxx address can be a completely legit thing.

Possibility is also that 3rd I/O map set is totally legit.
8245B CRT controller has the whole 8 bits wide access area in use.
If so then those 2 right side timer chips are pretty unknown.

3rd I/O map set has those RD things.
Only block diagram missing part is front panel encoder, but it's totally elsewhere and very simple.
Back panel has many input and output clocks, but all of those unknowns are RD, like read and so for input, or it can be Rear Data and so address 5F34xx is back as unknown.

*SOFTRST can be the upper timer on the right.
There are many things that can trigger it, like those clock chips.
So it can be a watchdog.

[stfjohn]

How do I figure out which is pin 5 of the 63484 from the copper side of the circuit board?

[m k]

The "dot" in the middle of the upper edge is index, so position 1 is above it.
Then normally counter clockwise, so 4th left is 5 and last is 9.

Seems that you must measure where that pin goes.

E,
I read that there are also non standard sockets.
Real or not, better do a measurement.

Standard goes so that last pin of a side has no pair and outer is smaller, but pin 1 moves to inner side when pin count goes low enough.
For 68 pins outer row of 1st side is for odd numbers, so 5 is 3rd from the end.

[stfjohn]

here is the scan as per your last post.

[m k]

That's a completely sane picture.
No chip is selected because address is 5F1Cxx and that position is empty.
So for now your problem seems to be a program error.

But maybe we can gain something from those _CS pins.
So change trigger one by one to POD 06 to 15 going low.
If it's triggered take a picture.

[stfjohn]

Trigger pod 06, 07, 08 : nothing changed.

[m k]

Pictures are rational and real I/O map seems to be quite different, so a pictured one can be only a principle map and for now program error is no more.
But now you must explain a bit how you made those pictures.
I was expecting that _CS POD line going down is visible.

We also know that CRT controller is accessed, so its _CS line goes down, but now it's missing.

Pictured addresses
5E00xx POD 13 32081 21 _SPC FPU
5E04xx 5E08xx 5E0Cxx

5E10xx 5E14xx 5E18xx 5E1Cxx

5E20xx POD 11 62421  2 _CS0 RTC
5E24xx
5E28xx POD 12 62421 15 _CS1 RTC
5E2Cxx POD 14 8279 22 _CS KBC

5E30xx 5E34xx
5E38xx POD 09 71054 31 _CS U86 timer
5E3Cxx

5F00xx
5F04xx POD 15 9914 3 _CE GPIB
5F08xx
5F0Cxx POD 10 68450 17 _CS DMAC

Missing
POD 06 63484 5 _CS CRTC
POD 07 71054 31 _CS U52 timer
POD 08 71054 31 _CS U67 timer

[stfjohn]

I took the measurements exactly as you suggested. The only doubt is that pin 5 of the 63484 is not the one in the photo where I soldered the strip...

[m k]

I'd put it to same position.
So for now a guess is that "no change" is CRTC.

Earlier stuff,
picture of reply #78, how was that triggered?

Lower part of ROM module, leave it if it's difficult,
connector side has probably some RAM chips, but other end has also something, more RAM chips or something else?

So I've been seeing things again.
ROM board J2, instead of up or down it's obviously connecting a pin of external something.

Can you easily connect a POD pin to ROM board HC240 pins 19 and 1?
It's for finding MODESET, just leave it if it's too complicated.

Can you scroll analyzer screen left and right, can you see somewhere that _CS POD pin goes down?

Few logic chip IDs needed.
Don't do it if you can't do it without dismantling the current setup, not that important.

1 left of DMAC and 5 under it, 1 is clear, rightmost seems to be 139.
1 right of FPU and 2 under it.
7 around a bottom right corner, the bigger one seems to be 74F something, but maybe not.

[stfjohn]

I did the scans again anyway, because I noticed that, for each trigger pod, the scan varies at least 4 times before stabilizing.

[m k]

Change trace mode to single.

You must get pictures where _CS POD signal goes down like POD 06.
Now we know for sure that this 5E10xx address is for CRTC, all others are unknown.
Addresses are possibly real, but they can't be connected if triggering POD signal is not going down.
There can be other addresses that have happened before or after trigger and are now in picture.

All pictures that are aborted are probably not triggered.
Others have the actual happening somewhere else, possibly later in data.