ADVANTEST R9211B

[stfjohn]

I asked the seller and this is the answer:

"this is the original Maintenance Manual for the R9211 Analyzer.
The pictures are only an abstract.
It is quite complete.

"QUITE"....

[stfjohn]

From the seller:
"I will not send any pictures of further schematics due to legal rights.
What I can do is to send pictures from the table of contents...
And again: this is the only official maintenance manual which Advantest ever released. You will find no other source.
The manual handels the following R9211 types: A/B/C/E/F
There is only an excerpt of all schematics inside not all! To my knowledge there is no existent repair manual with all schematics available and never was.
And again to make it clean:
This manual is the Maintenance Manual NOT the a Repair Manual!"

[squadchannel]

This manual is the Maintenance Manual NOT the a Repair Manual!"

Any test equipment since the 1990s that has gone digital is no longer basically a repair manual.

Anyway, as “B” is specified, I think it is a valid manual.
Since no one understands this error, I guess the only way to find out is to buy the manual.

[m k]

This manual is the Maintenance Manual NOT the a Repair Manual!"

An indication that the manual is partly a field maintenance manual.
It may include a mainboard schematics, maybe that SMPS also.
But bus cards, I doubt.

Maybe they followed HP route.
If so then some extra boot info is probably present.

[stfjohn]

I bought the manual in question. Let's hope it's of some use....

[stfjohn]

The manual arrived. Unfortunately it contains no diagrams except block diagrams. This is the only one of any interest, in my opinion.

[m k]

So you have few more or even more difficult routes.
Maybe easiest is to get a 68k hardware monitor and check how program flows.
One other could be a two channel timer or something like that to check how chip selects go, after every switch on you can guess what CS was later and so on.
Reverse engineering the whole software is of course also a route.

Block diagrams can be close to schematics, but there must be plenty and detailed ones.

If the above block diagram is a guide you can assume that the program bus is operational.
It also means that you can verify initialization of all of those upper side chips.

[stfjohn]

Forgive my ignorance on this matter: where can I find a 68K hardware monitor and how should I use it to check the program flow?

[m k]

Maybe it is no more.
Back in the day had a thing where special socket was put in between the CPU and its original socket.
The special socket was hooked to the monitoring machine and it did what was wanted or needed to figure out what was happening.

[stfjohn]

How can I verify initialization of all of upper side chip?

[m k]

You can start by scoping GPIB data lines.
If there is life you can expect some boot info.

Next you can scope all possible chip select signals, maybe you are lucky and only few appears.
Skip memories, they are tested or not and passed enough.
All parts don't need any actual initializing, but they still must, or should be found.

If you want to verify what is really happening you need to figure out what is coming and going.
For that one possibility is a logic analyzer, but it is much work for little gain.
And you still need to check all programming manuals to find out what all those things mean, and then find out that the program is actually doing exactly what it is suppose to do.

The block diagram indicates that there's only one pair of bus drivers, so data part is fine since CRT has meaningful text, that must go through the data part of the program bus.
All other parts are unknown, but can you decipher anything from the text on screen.

Maybe you should start from the assumed end.
One can assume that checking ROMs is so easy that it is done and failure would be indicated differently.
But if it happens to be so that lower part of the block diagram parts are getting attention does it mean that upper part is already done and ok.

TI DSP is a normal part so that is easy, but Advantest bus controller is trickier.

1st left memory block of the lower part of the block diagram, is it MEMCRT?
If so then check their _OE(16) pins, they are 8x memory chips left from bus connectors.
If _OE doesn't go down those memories are not used and text on screen is directly written to CRT controller.
If so then it's possible that the text on screen is not present in ROM in normal ASCII text form.

But this or that reading ROMs out is always beneficial.
In case you don't have a gear for that near by, don't use too much effort, it doesn't help you in near future.

In case you have hard times accessing pins when the machine is in one piece check those IC pin minigrabbers.

Some scopes have multiple triggers, if you want to figure out the initializing order of chips.
Simple dual D-flop circuit will do it also, there CS signal flips the other flop's set or reset, adding few LEDs is not a bad idea.
Then you just flip pairs to find out what is always later.

Chip select signals are multiplexed.
So following the trace back you should find from where it is coming, it is not a multi use signal, if not for multiple equal chips, like memory chips.
The problem can be also that multiplexer.

Checking (de)multiplexers and multi line transceivers can be tricky.
For that you may need a logic analyzer, and 8 bits is not very wide.
I'd probably skip MCU stuff, few latches and D-flops with LEDs are much more versatile for single purpose.
But there are so few peripheral program bus chips that you'd probably be fine with cheap 8 bit USB thingy.

[stfjohn]

I connected the GPIB socket to the computer, but no sign of life! Question: if the initial software is not installed, could it be a problem with the PROM - EPROM bank?

[m k]

Yes, but it's also possible that this part is not yet activated.
You can test the chip _CE pin 3, if it doesn't go down the chip is not accessed at all.
If there is some activity the chip is possibly initialized, but program is not sending anything.
You can also ask its ID.

CRT controller HD63484 _CS pin 5, you know it's active.
Maybe it is more easily accessible and can be traced backwards, if you want blindly change some chips.

I don't think that displayed text is from so early that only CRT is accessed.
How long is Diag Soft Level 0 description, can you put up some pictures?

I seem to have hard times understanding what can be originating a displayed text like that, if it's not on purpose.
It's like from a place where it is not suppose to happen and therefore not really being informative at all.

What kind of programming the machine has, is it always the same and in ROM?
The displayed text is similar to a software that has some unexpected part missing, like a wrong DLL with a missing function.
But static ROM image is very easy to verify.

Lower right corner of a ROM card of block diagram, is that marking a battery?
If that 128k RAM should have a program its integrity is also very easy to check and so shouldn't be a source for that displayed text.

Can you find any special resetting procedures from that manual?

[stfjohn]

The manual is 99% dedicated to the analog parts and power supply. The rest assumes that the self test works! Consequently the troubleshooting instructions absolutely do not provide for the initial program not to be installed! The manual is practically useless! The only other image of some interest is the one I attach now. No reset indication! What Diag Soft Level 0 description?

[stfjohn]

There is no battery in the ROM board. Perhaps the symbol indicates the electrolytic capacitor present

[m k]

Yes, probably a capacitor, just a left side of bottom part missing.

Diag Soft Level 0 is mentioned in your earlier logic 1 picture.
Its description should be just before that pictured page, section 3.2, maybe it's so brief that you've missed it.

68k CPU has a memory mapped I/O.
Means that it doesn't have any dedicated I/O instruction like x86 has.

68k has 24 bit address bus, or 23, it's always a word.
So highest bit defines data bus, you can check how it goes.
Then there is this that defines 0101 of highest nibble.
It can be one or two circuits, one is easy, just a chip with separated enable pin.
Next is this 111x nibble for I/O, all of this can also be a single PAL chip.

You can also forget those and concentrate to address bus directly.
If highest bit is active all the program bus should be done, per the text in logic 1 picture.

[stfjohn]

The section 3.2 is an analog portion.
There is no battery in the ROM board. Perhaps the symbol indicates the electrolytic capacitor present.
I noticed that one of the two LEDs present (D10) is not lit during operation (the LED in question is connected to p. 13 of the nearby 74F138 integrated circuit), while D3 is lit (probably indicating the presence of 12V voltage).

[m k]

Beside the LED D3 are TP1 and TP8, can you follow where they go?
I'm still after that boot info.

Can you find those other test points and diodes?
During the design process all numbers have at least been somewhere.

There seem to be many of those 138 3to8 chips.
Stacking them goes so that higher one is only an enable for the next level.
I/O area division in earlier picture indicates 3to8 chips.

Beside the 74F138 of D10 is 74F08.
Second order after 5 for I/O can be simple 4 input AND, or 3x 2 input AND.
Since 5E and 5F are both for I/O the last bit can be ignored.

If the LED D10 is indicating something special, like it most likely is, it can be for 3rd section of I/O area, then it would be 2 after 5F.
But is there something so special that an indicator LED is added, and just one for very sudden access.

For work area RAM the LED can be a preselector, so 010x of 2nd highest nibble, then it would include nibble addresses 4 and 5.
It can be even so that a watchdog something is written to addresses that blinks the LED and indicates that the software is not stuck or running away.

[stfjohn]

TP1 goes directly to the GPIB connector; TP8 connects to p.2 of the TL7700 IC (4+4 pins) immediately behind the GPIB connector.

[m k]

TL7700 is a voltage supervisor, so no boot info from there.

In theory a GPIB control pin could be an async serial connection, but that's a quite a bit of a theory.

Starting 68k goes so that first address is zero.
So you can scope its address bus directly and tell how things go.
For I/O check a 4 channel scope is enough.
A23 and A22 to check it's less than 8 but more than 3.
A19 and A18 to check it's more than x8, so after E2PROM.
Conditional trigger wouldn't be bad either.

[stfjohn]

The only signs of life I see on the 68000 are the clock 10 Mhz at p. 15 and the signal 1 Mhz at p. 20.

[m k]

The CPU is probably halted, pin 17 is down, if so then address and data are in high impedance state, so no more info from there.
But you can use it as an external trigger, if you can see few moments in history.
Even better if you can use it as a stopper.

Since the thing most likely does the same after every boot you are fine with dual channel scope.
Just stop collecting when halt goes down and check how those address lines were.
You may need to boot several times, but that is a small burden.

You can also build a simple circuit, single chip latch will do.
Pin 6 is address strobe, active low, address comes first and then _AS goes low.
So LS374 and output LEDs can be 8 bit status indicator and store the last partial address.
You also know that CRT controller is accessed, so something must blink or it doesn't work.
More complex it will become if you need to trace back unknown addresses, then this USB dongle logic analyzer is much easier.

[stfjohn]

I was loaned a logic analyzer...
Photo #1 pod 0 = P. 1 (68HC000) (the remaining pins to follow).
Photo #2 pod 0 = P. 16 (68HC000) (the remaining pins to follow).
Photo #3 pod 0 = P. 50 (68HC000) (the remaining pins to follow).
Photo #4 pod 0 = P. 33 (68HC000) (the remaining pins to follow).

[m k]

Picture 2 02 must be E pin 20, so pins 24 and 25 are down, interrupt is active.
Addresses A1-3 defines the interrupt, then other addresses are high, so that moment is history.
Pin 26 is high, so CPU is in supervisor mode and serving interrupts.

Picture 1 14 is clearly a clock, next is up so it's not GND.
07 is down, it can be _LDS and so 16 bit data operations.
A bit after center 08 goes down few times, those can be write cycles, same time data seems to be 0000.
A bit before center picture 2 has other supervisor data cycle, there data seems to be also 0000.
But the earlier cycle is read, so maybe there the CPU tries to clear the interrupt but fails.

Incoming data can be buffered.
Earlier block diagram indicates that only DMA controller is buffered, but those buffers should be drawn differently.
Maybe some other parts are completely missing.

[stfjohn]

I'm afraid there's very little that can be done unfortunately....