Interesting- SiC JFETs as the next-gen switching devices

[schmitt trigger]

This may be old news to some advanced folks here, but to me it was a revelation;

Looking for something unrelated, I stumbled into this white paper, which I believe will be of great interest to people interested in Power Electronics.
The WP’s name is a little misleading, as the real breakthrough IMHO, is the use of SiC JFETs as power switching devices. JFET devices are normally ON, so how do you use them for switching? With a cascode configuration, that is how.

Please comment. As I mentioned earlier, if these devices really deliver the performance gains and don’t have some weird failure mechanisms, they have the power (pun intended) to revolutionize the SMPS industry.
What do you think?

[Wolfram]

These parts have been available for at least some six-seven years from USCi/UnitedSiC, now owned by Quorvo. They are competing with plain SiC MOSFETs, from Wolfspeed, Infineon, Onsemi, ST, Rohm among others, also with a similar history of availability.

SiC power semiconductors really are as amazing as they seem, and a total game changer for high voltage power conversion. The first buck converter I made with SiC MOSFETs managed to do 16 kW with a pair of TO-247 devices with a die area of less than 7 mm^2 each. Efficiency was above 99 % at 800 V in, 450 V out and 10 kW power.

Price used to be an argument against SiC, but when working with DC bus voltages above 400 V and considering Rds_on losses at realistic junction temperatures, they are much cheaper than any silicon MOSFET technology I've seen. And considering the savings in magnetics due to being able to use higher switching frequencies with a given loss budget, it often comes out a lot cheaper from a systems perspective. A similar argument can be made regarding cooling system cost, SiC can operate with lower losses, higher junction temperatures and with less of a conduction loss penalty at high Tj.

[T3sl4co1l]

I'm of the impression they're the older technology.  They were the first type to release, I think.  Not to say they're falling behind or anything; they've been asymmetrical* from the start (by necessity), and have incorporated SJ since then, I think.

*That is, max Vgd != Vgs.  This just to contrast with the typical (diffused? lateral?) Si JFETs familiar for signal purposes, which are generally symmetrical, or close (think I saw one that's 20 vs. 40V or something like that?).  And that itself is more an accident of Si JFETs in general: there used to be higher voltage types, but they disappeared quickly as BJTs were improved.  So you only see small-signal JFETs left these days.  And not many, at that...

There's also some SiC BJTs, which bizarrely they specify them like they're FETs with "gate" current... I don't even. Do people not know how to use BJTs anymore?..

Anyway I digress.  The hybrid cascode ones are fine, at least from the data I've seen; I haven't used one yet.

There's also hybrid cascode GaN devices, basically so you get the same Si compatible drive level.

Cascodes reduce reverse transfer capacitance a bit.  In particular, Crss above [voltage] saturation is minuscule.  Which means output dV/dt has almost no bearing on gate resistor for example, and you're only tweaking dI/dt (and fairly crudely at that) as a result.  So keep that in mind when tweaking for EMI response.  Capacitance is still quite large at low voltages however, because the cascoded device saturates, exposing the bottom transistor's capacitance.  So it's kind of like SJ turned up to 11, an even more extreme abruptness of capacitance variation.

And mind, capacitance variation isn't necessarily a problem.  It's mainly troublesome for hard switching applications, where one transistor turns on into the other's (very large capacitance, because its voltage is still low), which acts very much like reverse recovery of a PN diode.  It's not, it's a majority carrier effect, like a schottky diode -- but the large capacitance still incurs dynamics in the switching loop which have a very similar effect in the end.

Anyway, they're fine.  They exist because you don't need to know anything special to use them, just take note of the particular characteristics (Qg, Coss, speed and losses, voltage limits, etc.).  They probably perform slightly worse than single devices, on account of added Rds(on) from the series device, and perhaps there is reason to more tightly control the main device's Vgs -- but to do that you need SiC or GaN specific drivers, so the space of gate drivers you can use with it is greatly reduced.

Tim

[schmitt trigger]

As I had mentioned, I wasn’t previously aware that these devices had already existed for 7+ years.

Although the WP is glowing with respect to SiC JFET’s capabilities, if they have not become mainstream in this period, is because there are caveats to its use, or people don’t understand them sufficiently to apply them correctly. Or both.
Which one of those scenarios is the root cause? I don’t know. But the devices themselves are quite intriguing.

[Wolfram]

Tim hits the nail on the head (as usual). Main issues being resistance contribution from the Silicon low-side MOSFET, particularly at high temperatures, and lack of control of drain dV/dt by Rg are the main downsides of this technology compared to plain SiC MOSFETs. For the latter, USCi recommend using a drain RC snubber (AFAIU for functional reasons, not just EMI) with these parts. When I compared them for a commercial project, cascodes were just not competitive for our application comparing Rdson at temperature. That was a few years back and for 1200 V devices, I remember the 650 V parts looked like a better value proposition compared to other options.

One of the main marketing points for these is drive compatibility with Silicon MOSFETs and IGBTs, and I can see the advantage of this. I could see them being interesting as drop-in replacements for superjunction in 650 V applications, but this is also less of an advantage at 1200 V where IGBTs rule. Just plain substituting IGBTs for SiC in a given application is not likely to lead to a very optimal design, most of the cost and size savings are realized when magnetics are resized to rebalannce converter losses considering the usual ~85 % reduction in hard-switching losses compared to IGBTs.

One could argue that the support for GDT drive can reduce thee cost and complexity of the drive system, and this applies in some, but fewer and fewer cases. Duty cycle range with GDTs is limited on account of the volt-seconds balance, so it's mainly relevant in resonant or narrow-duty-cycle range applications. With the slew rates of SiC (and also SJMOS), current injection into the driver stage through GDT interwinding capacitance is a real concern, generally in the 50+ V/ns range. Fully isolated gate drive chips with UVLO, dead-time enforcement, good CMTI (150++ V/ns) and low cost are plentiful these days, the same goes for low-capacitance CMTI-characterized DC/DCs for gate drive power.

The devices have had success in the market, maybe not as much as plain SiC MOSFETs, but I have seen units in the field as part of mass produced DC EV chargers.

They also do plain JFETs which are pretty interesting. They don't have the Rdson contribution from the cascode FET, but they are also a bit tricky to incorporate into robust voltage-mode converter topologies as they turn on when gate power is lost. For current-fed topologies, they could be an excellent option though. I also recall hearing that they are good for protection circuits like solid state DC fuses, as their saturation behavior is more abrupt than MOSFETs, limiting current to a larger degree during overcurrents for a given voltage drop at nominal current.

[T3sl4co1l]

They also do plain JFETs which are pretty interesting. They don't have the Rdson contribution from the cascode FET, but they are also a bit tricky to incorporate into robust voltage-mode converter topologies as they turn on when gate power is lost. For current-fed topologies, they could be an excellent option though. I also recall hearing that they are good for protection circuits like solid state DC fuses, as their saturation behavior is more abrupt than MOSFETs, limiting current to a larger degree during overcurrents for a given voltage drop at nominal current.

Also interesting is that a lot of them (MOS and JFET) offer DC SOA, making them very interesting for pulsed application. Not very much duration still, because we're talking IMMENSE power levels at these voltages, but enough to get some things done.  It means in something like a switching current limiter, you can be a lot looser with gate drive speed perhaps.

Kind of less interesting, is the incredibly small die area on these.  Very thin, lots of current density.  So there's very little power dissipation or avalanche capacity for short time scales, and at longer time scales it's all about the backplate / tab.  Which is still a fair amount of power (100s, maybe 1000s W) in the relevant time scales.

As for economics, I can't speak for that. They're certainly available; early on, they were specialty parts you'd probably need an NDA from the mfg to even look at the datasheet; now, they're readily available at DK etc.  Prices have come down and are quite competitive at high power (some kW?).

It also speaks to just how far Si alone has come; it's not going away any time soon.  So you have SiC for high voltage and power, GaN for high speed and low to medium voltage, and Si for everything else.  There's a lot of applications where you just don't need much, and Si will always serve that; much as CD4000 and 74HC logic aren't going anywhere, they're too useful to discard, even if not used as much these days. 

Tim

[boB]

I   love  our SiC  FETs.  Standard 650V non-cascode.

I also noticed from a United SiC data sheet, the increased RdsOn with temperature and attributed that to he series silicon FET.

I did not see that disadvantage in the USic paper.  But if the  RdsOn is half of a regular non-cascode SiC FET, then maybe that doesn't really matter much as long as they are the same price.

Our 650V SiC FETs work great and are easy to drive.   The price was low enough to use but now, the prices are rising again, maybe because of all the increased usage by auto companies ?

Great stuff !

boB

[mtwieg]

I've been working with WBG semiconductors for >10 years (mainly GaN, a bit of SiC), and it seems adoption of WBG technology is slow because designers want to have their cake and eat it too. They really want the higher power density, but also want the new device to be a drop-in replacement without any significant changes or risks to the rest of the design or product. I'm assuming I don't have to explain how silly that is.

The most bizarre WBG part I've seen is the GaN FETs from Transphorm which come in TO-247 packages. I'm certain they chose a familiar package so that designers would feel more comfortable substituting it into existing designs. But now you have a super-fast FET trapped in a package with lots of parasitic inductance. Which is likely why Transphorm heavily recommends using RC snubbers and also a ferrite bead on the gate (thus crippling some of its performance gains over Si).

The value of WBG devices depends on how much you're willing to take advantage of them. New packages, new gate drivers, new magnetics, new thermal management etc. When faced with that, a lot of designers lose interest. I'm not saying they're dumb or lazy, it's often the correct choice for their particular product/application.

Our 650V SiC FETs work great and are easy to drive.   The price was low enough to use but now, the prices are rising again, maybe because of all the increased usage by auto companies ?

Last year our FAEs for Arrow advised me to be wary of using SiC for new designs, as lead times were expected to spike severely. I'm guessing it's mainly due to automotive, the high temperature performance of SiC is perfect fit for them. Not just for the giant semiconductor modules in EVs, but also lower power systems in more conventional vehicles (48V systems like electronic steering).

[Wolfram]

The main issue I had with JFET cascodes in the 1200 V class is related to cost vs. performance compared to MOSFETs. On a first glance, they look very competitive in terms of cost*Rdson, switching loss and gate charge, but the available devices have a significantly higher temperature coefficient of Rdson than the MOSFETs I compared it to. Once the device is scaled to compensate for this, the advantage is not really there any more. This conclusion does not hold for all cases, the relative merits depend on the application requirements and the pricing you happen to get from your distributor, so I could see cascodes being favorable in some cases.

As regards to SiC lead times and availability, this has been problematic for a while and it looks like it will continue to be so for a while, but I don't think the situation is hopeless. Comparing to just a couple of years ago, many more manufacturers are launching devices now, and most of the established manufacturers are expanding capacity. Wolfspeed's new Mohawk Valley fab is still in the production ramping phase, with a target capacity of multiple times the older Durham plant. They are also expanding wafer capacity by almost an order of magnitude, which is a huge deal since they supply raw wafers to most of their competition as well. Then there's an even larger plant being built in Saarland in Germany, so production capacity will increase massively in the medium-long term. Demand is also increasing a lot, but hopefully the supply situation will be better in general from next year.

[JohnG]

I've been working with WBG semiconductors for >10 years (mainly GaN, a bit of SiC), and it seems adoption of WBG technology is slow because designers want to have their cake and eat it too. They really want the higher power density, but also want the new device to be a drop-in replacement without any significant changes or risks to the rest of the design or product. I'm assuming I don't have to explain how silly that is.

The most bizarre WBG part I've seen is the GaN FETs from Transphorm which come in TO-247 packages. I'm certain they chose a familiar package so that designers would feel more comfortable substituting it into existing designs. But now you have a super-fast FET trapped in a package with lots of parasitic inductance. Which is likely why Transphorm heavily recommends using RC snubbers and also a ferrite bead on the gate (thus crippling some of its performance gains over Si).

The value of WBG devices depends on how much you're willing to take advantage of them. New packages, new gate drivers, new magnetics, new thermal management etc. When faced with that, a lot of designers lose interest. I'm not saying they're dumb or lazy, it's often the correct choice for their particular product/application.

This is absolutely the case. An analogous situation occurred with the appearance of the silicon power MOSFET. Everything had to change to take full advantage of them, but most of all the designers had to pay attention to stuff they never did before. It did change, though, and revolutionized power electronics and arguably is as significant as the development of CMOS microprocessors (though less glamourous).

John

[T3sl4co1l]

The main issue I had with JFET cascodes in the 1200 V class is related to cost vs. performance compared to MOSFETs. On a first glance, they look very competitive in terms of cost*Rdson, switching loss and gate charge, but the available devices have a significantly higher temperature coefficient of Rdson than the MOSFETs I compared it to.

Oh yeah, that's a weird thing, that I'm not sure I know of an explanation for yet.

Maybe SiC allotrope?

Have seen some MOSFETs with nice low tempco, like, as much as you'd expect from silicon but over the temp range SiC can handle, so, over the 175C range it's real chill.

Others, it's actually worse and like, why are you selling this, it has hardly any advantage. Still faster I guess??

Also, some MOSFETs randomly have (or had?) stupendously high gate spreading resistance?  Like, they're slower than Si despite the lower Qg?  Most these days are quite modest (10s ohms?) so it's not an issue, but yeah there's been some oddities there.

I haven't looked at enough JFETs to know if the same parameter spread appears among them.

Affects schottky too I think? But those have improved (since the earliest days) due to die backside thinning or whatever, at least.  Hm, not sure if they're made in different allotropes, and what the tradeoffs are if any.

Tim

[analityk]

Try to find some HEMT devices. They are faster than any SiC and you can buy 40 A/ 100 V device with 10nC total gate charge and drain resistance as small as 0.0035 ohms and it is driving from 5V. All of this in 3.5 X 2.35 mm chip. (GAN3R2-100CBE NEXPERIA)

[mtwieg]

GAN3R2-100CBE NEXPERIA

Huh, wasn't aware Nexperia was making low-voltage GaN devices. This one seems like a straight carbon copy of the EPC2218, footprint compatible too (except the die is much thinner?). Wonder if they'll add more variety to their low voltage portfolio in the future.

For operating voltages <200V, GaN seems to be a far better option than SiC.

[ArdWar]

Was somewhat excited by Nexperia's "No body diode" claim, turns out it's the exact same thing as EPC's "Zero Q_RR"claim.
Thing's still conduct with negative V_DS. I guess it's technically not conducting through body diode nor any diode-like mechanism but still..

[mtwieg]

Was somewhat excited by Nexperia's "No body diode" claim

Yeah that's a pretty silly thing to put at the top of a datasheet, even if it is technically true. I hope nobody read that and actually assumed it would block in the third quadrant.

turns out it's the exact same thing as EPC's "Zero Q_RR"claim.

This on the other hand is just true (though maybe it depends on how exactly you define Qrr).

[T3sl4co1l]

Was somewhat excited by Nexperia's "No body diode" claim

Yeah that's a pretty silly thing to put at the top of a datasheet, even if it is technically true. I hope nobody read that and actually assumed it would block in the third quadrant.

Who are you to say it doesn't?

It's an asymmetrical FET, of course you don't get much range in inverted mode.

Tim

[tszaboo]

I've been working with WBG semiconductors for >10 years (mainly GaN, a bit of SiC), and it seems adoption of WBG technology is slow because designers want to have their cake and eat it too. They really want the higher power density, but also want the new device to be a drop-in replacement without any significant changes or risks to the rest of the design or product. I'm assuming I don't have to explain how silly that is.

The most bizarre WBG part I've seen is the GaN FETs from Transphorm which come in TO-247 packages. I'm certain they chose a familiar package so that designers would feel more comfortable substituting it into existing designs. But now you have a super-fast FET trapped in a package with lots of parasitic inductance. Which is likely why Transphorm heavily recommends using RC snubbers and also a ferrite bead on the gate (thus crippling some of its performance gains over Si).

The value of WBG devices depends on how much you're willing to take advantage of them. New packages, new gate drivers, new magnetics, new thermal management etc. When faced with that, a lot of designers lose interest. I'm not saying they're dumb or lazy, it's often the correct choice for their particular product/application.

It's usually not because of the design hurdle. It's because of vendor lock-in. Once you select devices with unusual vendor specific packages, you are stuck with it. SiC was especially troublesome, as it was coming from small manufacturers and some of them disappears if the wind is blowing the wrong way. And you are stuck with a design, halfway through certification that you cannot build.

[mtwieg]

It's usually not because of the design hurdle. It's because of vendor lock-in. Once you select devices with unusual vendor specific packages, you are stuck with it. SiC was especially troublesome, as it was coming from small manufacturers and some of them disappears if the wind is blowing the wrong way. And you are stuck with a design, halfway through certification that you cannot build.

Certainly the prospect of devices becoming suddenly unavailable is going to discourage a lot of engineers, especially for designs requiring long term support. Same was true when power MOSFETs were starting to replace BJTs.

But of all the differences between MOSFETs and GaN/SiC FETs, packaging is relatively trivial compared to electrical characteristics. Again, much like how MOSFETs were coming in TO-220 packages while most engineers were accustomed to BJTs in TO-3 style packages.

[Kevin.D]

Was somewhat excited by Nexperia's "No body diode" claim

Yeah that's a pretty silly thing to put at the top of a datasheet, even if it is technically true. I hope nobody read that and actually assumed it would block in the third quadrant.

Who are you to say it doesn't?

It's an asymmetrical FET, of course you don't get much range in inverted mode.

Tim

I obtained a few of these about 4 years ago first assuming  they where somewhat symmetrical ( just noticed manufacturer site chose the symmetrical JFET symbol for their JFETS  (of the two JFET schematic symbols available I always thought the one with gate to the center of channel supposed to signify symmetrical and the other JFET symbol with gate offset to source was for an asymmetrical device). Back then was going try them  in a simple Bidirectional (AC) Eload I had in mind which  obviously have some advantages over unidirectional devices . After having a good look at the data sheet again though I noticed the max Vgs (-25 V) which signifies it must be asymmetrical.
I decide to go ahead and see what useful working range if any could get from them when operated in inverted mode anyway, After a few simple bench test's I found they could be used
upto about -50 Vds, above that reverse leakage through Vgs got to much and latched them on (I had read a white paper on these somewhere on the web  which mentions that that the g-s junction was self healing when subject to over voltage and high leakage current so unlike a BJT e-b junction it shouldn't cause lasting harm the junction) .
Things I noted though operating in inverse mode they had a reduced gm (about half to a third of forward gm but still supposedly useable for my purposes). Interestingly when characterizing I discovered the Vgs(th) actually had a POSITIVE temp coeff when operating in inverse mode ( it had the usual negative temp-coeff in forward mode) . Anyway I was hoping for a bit more than 50 V operational range I got so disappointed , but probably could still be used for a simple lower voltage/lower power AC adjustable load (it saves having to have twice the number of dissipating elements one oriented for each current direction but then they are (or where) twice as expensive as Si MOSFETS), you could use it singularly if less 50 V ac or if higher AC voltages handling required then maybe paired with  another in a cascoded/series setup (where the top SiC JFET is in forward mode dropping most of the Voltage) and  the bottom controlling JFET (oriented in reverse mode dropping up to 50 V so still dissipating some share of the power), then during the negative going current cycle the two JFETS would exchange modes, a bit obfuscated yeah but would work. Veering off topic sorry

[mtwieg]

I obtained a few of these about 4 years ago first assuming  they where somewhat symmetrical ( just noticed manufacturer site chose the symmetrical JFET symbol for their JFETS

What specific device are you referring to? In my last posts I was referring to GaN FETs, but I'm guessing you're referring to some SiC JFET.

After having a good look at the data sheet again though I noticed the max Vgs (-25 V) which signifies it must be asymmetrical.

Just curious, what about that implies they're assymetric?

Veering off topic sorry

No worries, it's interesting stuff. Just curious why not just use a pair of normal MOSFETs connected in antiseries?

[T3sl4co1l]

What specific device are you referring to? In my last posts I was referring to GaN FETs, but I'm guessing you're referring to some SiC JFET.

In regards to the topic I suspect (SiC JFETs), though those too.  I haven't seen GaN with less than -6V Vgs, I think; or maybe not even below 0, I forget.  Clearly they aren't symmetrical devices either!

Just curious, what about that implies they're assymetric?

A traditional (diffused?) JFET is symmetrical in that S and D are formed by diffusion (or epitaxy or implantation, whatever works) around a G substrate.  Neither of the present technologies is symmetrical, and likely they specialize further, like having Vds dependencies (as most VDMOS do), rather than Vgd/Vgs (as JFETs or lateral MOSFETs might have).  Obviously, there isn't any way(?) to make a symmetrical 600V something or other, and it would have pitiful gain even if it did (gate operates on channel through huge depletion region), so just one side is made wider and lightly doped as the intended drain.

GaN are a bit something else, because they use a remarkable bit of physics (2DEG) which can probably only be fabbed as a lateral structure, but it's so much more effective than a regular FET that it hardly matters.

SiC is generally like an improved Si for higher voltages, and AFAIK they have all the traditional structures available that are used in Si (except maybe SJ, but it's not relevant in commercial rated MOSFETs i.e. up to 1 or 2kV), so you get JFETs, BJTs, MOSFETs and IGBTs for example, and I even saw an SCR the other day (which was very boutique priced, but definitely had a few advantages, like high forward and reverse voltage rating, and quite fast turn-on).  I think there aren't many ICs in SiC yet, but the planar process is there if anyone needs it (and I'm sure borehole, military and aerospace are deeply contemplating these possibilities).

At least in normal FETs, lateral vs. vertical is fairly easy to tell apart because of the predominant voltage dependency: lateral capacitances are dependent on Vgs (mainly Ciss varies strongly with Vgs, probably Coss does too, as well as varying with Vds due to ordinary substrate depletion), while vertical capacitances are dependent on Vds (Ciss is almost completely independent of Vds, with the only contribution being Crss which is the fraction of Coss where field lines terminate into G rather than S/SS; hence Crss and Coss vary in the same way).  An interesting consequence of this: a vertical MOSFET can be used as a surprisingly linear variable capacitor, if G-S is used as the capacitor, if it's biased to avoid turn-on (so, Vgs(min) < Vgs < Vgs(th), say -30 to 2V), and Vds is biased to adjust capacitance.  Of course since only Crss is changing, it's not a big effect, but it is linear (not dependent on Vgs).

I suppose for GaN, the capacitance voltage dependence doesn't matter much, because you have such a narrow Vgs working range.  So, it just is whatever the datasheet says it is.

Tim

[nimish]

These have been around for a while, including the elusive normally off e-mode non-cascode SiC (V)JFET: https://ieeexplore.ieee.org/document/5433483 and http://dx.doi.org/10.1109/ISPSD.2009.5158070 for example. Same tricks as in junctionless transistors and e-mode HEMTs where you manipulate the structure to have the transistor off at 0V (by fully depleting the channel (?) via work functions I think) but I don't think you get the wacky ohmic contact GIT or Schottky diode gate behavior you see in commercial GaN HEMTs.

SemiSouth, unfortunately, went under since they were a decade too early.

The authors of electronics books ought to have updated them to not claim that there are no e-mode JFETs anymore....