Hi,
Why do all the datasheet and app note schematics of high power offline flybacks with FSCQ1565 cotroller show no primary clamp whatsoever?
They only show a small Drain source capacitor, which they call the "resonant capacitor".
(which is true but it hardly seems big enough to quench leakage spiking for cases of overload, etc)
The internal FET is only 650V rated.
FSCQ1565 datasheet (pg 19 schem)
https://www.onsemi.com/pub/Collateral/FSCQ1565RT-D.pdfApp note for FSCQ1565 (AN4146) (pg 19 schem)
https://www.onsemi.com/pub/Collateral/AN-4146.pdf.pdf
Two example values they give are 680pF and 1000Pf. Do you have any leakage inductance and primary current figures that can be played with?
Perhaps its a balance of better control of fet turn-off for all modes of operation, and the anticipated leakage inductance in the application examples, and the schems show the drain cap on the winding terminal with a ferrite bead on the drain link.
The example schems in the datasheet and app note show a 83W offline flyback with no primary clamp, and this is very inadviseable....if not totally out of order.
At the very least you need a diode_TVS overvoltage clamp on the primary....and they show nothing like that.
The internal fet in the FSCQ1565 can avalanche, but its datasheet gives no repetitive avalanche rating, so therefore you cannot rely on avalanche of the internal fet to clamp the leakage inductance spike.
The internal fet of the FSCQ1565 is only 650V rated so this to me is a bad idea.
Also, coffeefet is onto a looser here, because page 13 of the FSCQ1565 datasheet says that adding the drain_source capacitor is good for EMC.
This just is not correct, because it worsens EMC due to the fact that when the FET turns ON, the drain_source capacitance is suddenly discharged, resulting in a discharge current spike which worsens EMC.
The datasheet says that the slower rising drain voltage at FET turn-OFF reduces EMC problems, but it doesnt , because it worsens EMC at FET turn-ON time. You cannot reduce EMC problems in a flyback by simply adding a drain source capacitance....if only life were so easy.
treez your comments are just prejudices based on past experiences with different converters. Actually build the converter being used as an example in the datasheet, before lambasting a particular implementation - the device has been out for 7 years now. Also read the datasheet about the QR suppressed FET turn-on transition loss technique - that technique has been around for about 2 decades, and seems to continue to be improved. The example circuit uses typical emi filtering, in-rush and 220uF to assist soaking up mains glitches, before a 50V margin on the min guaranteed Vds with max 230V+15% mains.
The thing is this is a fact as follows......from page 14 of the FSCQ1565 datasheet, it is evident that at maximum load, the switching frequency must be less than 45kHz, otherwise the converter will get stuck in "extended quasi resonant operation".
That is a very big restriction and means a large transformer will be needed.
The main point is that the AN4146 App note is showing FSCQ1565 offline flybacks up to 100W being implemented with no primary clamp whatsoever. This is not considered to be adviseable by i believe the majority of the SMPS fraternity across the world.