Small decoupling caps (100n) should fit inside / under DIP IC sockets.
Yes, i considered doing that but changed my mind when I saw the price of the sockets with a cap incorporated - I don't have any axial lead 100nF caps in the parts bin to check the idea but I think that there would be enough space by the pin shafts of a turned pin socket to carefully wrap the leads around on the diagonal and then solder it to the corner pins. I might try that if I need to go tighter on perfboard any time.
What I do have in the parts bin is a load of rectangular 220nF caps.........
Perhaps you could take the single-step circuit and put it on a separate small board and plug it in only when you need to debug?
You just need a small header for it to connect to. That may free up a couple of ICs worth of space.
I'm comfortable with the existing layout for now, hopefully that will not prove to be over-confidence.
haha, respect! you must like pain though ;-)
I would wire wrap this myself - if I *had* to do it this way.
Or, honestly - maybe just go straight to PCB and save an absolute crap load of time (only to spend it on something else after of course).
You could use free diptrace and modularise it maybe? I didn't study the design, but core CPU and memory on one card, then a ribbon to an IO card maybe? it would save you a world of pain, donny.
I agree that doing it on a PCB would be much nicer, for one thing I could use SOIC packages for the glue logic which would save a load of space.
I'd quite like to validate the design before trying to design a PCB.
Having built cards this way before it is not too painful - no harder than wire-wrap and you don't end up with enormously long pins sticking out of the bottom. Also I could choose not to bother socketing the TTL if I were very confident that it would work first time.
Would doing a PCB design save me time? Not sure. I'd have to layout the parts, that bit does not go away, then I'd have to route it which might well take longer. While I try to lay the wire moderately neatly you can just do it point to point "rats nest" style without worrying about crossings.
If I were to want to do a 2nd or a 3rd one exactly the same then designing a PCB would win hands down, obviously.
Would I want to do another - not sure. If the card actually works (and I'm not, TBH, sure about the memory timing[1], nor the CF card timing[2]) maybe it would be worth it just for the practice in designing and getting PCBs made up.
[1] There might be too much gate delay through the adders, especially as I used two cascaded, even with a wait state given that I am using 55ns RAM. The ROM should be OK as its addresses don't go through any mapping so I can hopefully write code to check the RAM.
[2] At 20MHz the length of IORD or IOWR pulses (about 125ns) will be significantly shorter than specified for PIO mode 0 timing (165ns), especially in 8 bit mode (290ns) but I don't think that this matters. I can't see that the card "switches" modes, they just have a fastest mode and thet is what the timing is. If I plug in a card which only supports PIO mode 0, 1 or 2 then it probably won't work. Otherwise it should be OK. Simples