@MIS42N
quoted text snipped for brevity to make up for my far from brief reply
I'm not quite sure how your failure case would look like exactly, but a simple XOR PLL obviously cannot deal with a GNSS outage situation at all. As soon as the time signal stops, the control voltage would either become 0 or "VDD", depending on the state of the XOR output. Keeping the time signal running with no GNSS coverage is useless of course, as the output would not be more accurate or stable than the receivers internal reference.
But of course the phase of the output would return to exactly the same offset as before, why wouldn't it? That offset is pretty much defined by whatever duty cycle of the phase comparator (and thus \$V_{tune}\$) represents the target frequency exactly. It would change over time with the aging of the OCXO.
Not only ageing but also a surprisingly sensible ambient temperature effect on the frequency stability of the OCXOs I'm using (I now see the point of using DOCXOs
) This manifests itself as a shift of a few hundred μV on the median operating point of the gps disciplining voltage variations holding the ocxo on frequency.
Looking at the datasheet for the 74HC(T)4046A, it seems the other two PDs (PDs 2 and 3) are really only appropriate to keeping a full frequency range VCO locked to a reference frequency - PD1, the XOR detector is the only one suited to this application, keeping an OCXO with its extremely tiny tuning range (a few ppm at most) locked to the averaged long term timing stability of a GNSS. Also, according to the data sheet, the output will rest at half the Vdd voltage in the presence of noise (which includes the 4Hz PPS frequency I'd programmed the U-Blox to emit during a loss of GPS timing lock) or absence of input to the Sig input pin.
I'd thought I might be able alter the duty cycle of this 4Hz pulse to more closely approximate the required EFC to hold the unlocked OCXO frequency closer to the 10MHz than it otherwise does but this proved to be ineffective since it effectively equates to the "noise" condition regardless of duty cycle.
The simple XOR detector (and its software equivalent) is the best option in this case. Of course, the phase displacement whilst locked will vary due to both ageing
and temperature effects but by how much is a question I've yet to try and find an answer to.
I'm primarily interested in the magnitude if this phase displacement due to the 3 to 5 degree changes in room temperature since, if this amounts to more than 2 or 3 ns's worth, it'll confuse my frequency stability measurements against the GPS reference since comparing the variation of phase between the ruby and the GPSDO is the only practical way I have to measure frequency drifts at 10MHz that are now down in the μHz range.
My impression of this temperature related shift in phase is that it is well below 5ns, quite possibly less than a ns or two at most but that's only a 'gut feeling' from my observations so far.
I've figured out a way to test my collection of OCXOs for this temperature effect. It's really only a matter of bread boarding a test circuit using a 74HC4046A and a couple of 74HC390s, to divide the ruby and the OCXO frequencies down to 100KHz, , including the LPF values in the feed to the LMV538 cmos RRO opamp that drives the OCXO's EFC pin, to simulate the setup used in my gpsdo but without the troublesome variations inherent to any GNSS derived timing signal.
That setup will give me a fixed phase relationship for a constant temperature applied to the OCXO under test (I could actually use another OCXO held to a constant temperature instead of the ruby), allowing me to test its temperature sensitivity independently of all the other effects in the gpsdo itself. It's just a matter of getting a "round tuit" to set it up.
Although the effect of ambient temperature on the GPSDO's OCXO seems an insignificant one (it gets swamped by the disciplining process), I might find an example in my collection (seven in total) with a much lower tempco that I can swap out to reduce this effect even further.
That being the case, I've even more motivation than merely satisfying prurient curiosity as to the magnitude of this phase offset variation with temperature, to actually put the effort into carrying out this test. I might discover a particularly good example with excellent immunity to ambient temperature changes that will allow me to use an even longer time constant PLL filter to reduce the disciplining induced phase shifts even further.